A SOI-RF-CMOS technology on high resistivity SIMOX substrates formicrowave applications to 5 GHz

A silicon-on-insulator (SOI) RF complementary metal-oxide-semiconductor (CMOS) technology for microwave applications up to 5 GHz has been developed. The technology is based on ultra large scale integration (ULSI) CMOS processing using a high resistivity separation through implanted oxygen (SIMOX) substrate of typically 10 kΩcm. Dedicated RF n-channel and RF p-channel MOSFET's with an effective channel length of 0.20 and 0.40 μm have been fabricated using a multiple gate finger design. Maximum frequencies of operation f _max of 46 GHz (NMOS) and 16 GHz (PMOS) have been measured. Metal-Insulator-Metal (MIM) capacitances with up to 63 pF with 70 nF/cm ², planar inductances with up to 25 nH and a quality factor up to 12 and coplanar waveguides with a loss <2.8 dB/cm at 5 GHz are monolithically integrated in the technology without additional processes and materials. Using this SOI-CMOS technology we have fabricated integrated silicon RF circuits, e.g., amplifiers, oscillators, and mixers, operating in the 2 GHz range     

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance R/sub G/, the metal T-gate FD-SOI MOSFET achieves a higher f/sub max/ of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower f/sub T/ of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances C/sub gs/ and C/sub gd/ respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.     

Design of a 0.18 μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier (LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91 × 0.53 mm2 while the total die area with ESD is 2.45 × 2.36 mm2.     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

数字硅MOSFET微波特性的研究

利用国内先进的 0 .6μm数字 Si-MOS工艺 ,设计了射频 MOSFET,并研究了其 DC和微波特性 :I-V曲线、S参数、噪声参数和输出功率。研究发现 ,数字电路用 Si MOSFET的频率响应较高 :频率为 1 GHz时功率增益可达 1 0 d B,2 GHz时为 8d B,4GHz时为 5 d B。 1 .8GHz时 ,1分贝压缩输出功率 1 2 .8d Bm,饱和输出功率可达 1 8d Bm,且最小噪声系数为 3 .5 d B。用提取的参数设计并研制了微波 Si MOSFET低噪声放大器 ,以验证MOS器件的微波性能。此放大器由两级级联而成 ,单电源供电 ,输入输出电容隔直。在频率 1 .7～ 2 .2 GHz的范围内 ,测得放大器增益 1 5± 0 .5 d B,噪声系数 N F<3 .8d B,1分贝压缩输出功率 1 2 d Bm;在频率 1 .5～ 2 .5 GHz的范围内 ,放大器增益大于 1 3 d B。     

A 15-Electrode Totally Implanted Time-Multiplex Telemetry Unit

A 15-electrode totally implanted time-multiplex telemetry unit is described that is powered by two mercury cells in series. Transcutaneous radio frequency (RF) turn-on and magnetic turnoff are used to conserve battery power. The basic cycle rate is 400 Hz, channel rate 6400 Hz. The channel 16 input consists of a 200-Hz 5 mV peak-to-peak (p-p) reference signal, and a 3200-Hz sync signal is added to all channels. The unit is1.5 times 2.5 times 8cm in size, weighs 41 g, and draws 3.5 mA. Low-frequency cutoff is at 0.2 Hz. The output is FM with a peak deviation of 75 kHz of a 20 MHz carrier at 5 mV peak channel input. The equivalent noise input is 2.8 μV root mean square (rms). The decoder automatically locks on the reference signal square wave with the aid of an exclusive-OR gate.     

Fabrication of Si MOSFET's using neutron-irradiated Silicon as semi-insulating substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The mobility of carrier in the channel is about 100 cm²/V . s for p-channel MOSFET's and 300 cm²/V . s for n-channel devices. This structure has inherent advantages such as crystallographically single crystalline.     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.     

Advanced thin-film silicon-on-sapphire technology: microwavecircuit applications

This paper reviews the prospects of thin-film silicon-on-sapphire (TFSOS) CMOS technology in microwave applications in the 1-5 GHz regime and beyond and presents the first demonstration of microwave integrated circuits based on this technology, MOSFET's optimized for microwave use, with 0.5-μm optically defined gate lengths and a T-gate structure, have f_t values of 25 GHz (14 GHz) and f_max values of 66 GHz (41 GHz) for n-channel (p-channel) devices and have noise figure values below 1 db at 2 GHz, some of the best reported performance characteristics of any silicon-based MOSFET's to date. On-chip spiral inductors exhibit quality factors above ten. Circuit performance compares favorably with that of other CMOS-based technologies and approach performance levels similar to those obtained by silicon bipolar technologies. The results demonstrate the significant potential of this technology for microwave applications     

一种射频可编程N分频器的设计

提出了用射频CML技术设计的2/3分频单元.基于2/3分频单元,使用0.35 μm SiGeBiCMOS工艺,实现了射频可编程N分频器.验证结果表明,电路可在GHz频率下正常工作,具有相噪低、功耗小等特点.在3 GHz射频输入信号频率下,频偏100 kHz的输出相位噪声为-143dBc/Hz.电路消耗的总电流仅为4 mA(3 V单电源电压),功耗仅为12 mW.     

Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The, mobility of carrier in the channel is about 100 cm/sup 2//V /spl dot/s for p-channel MOSFET's and 300 cm/sup 2//V /spl dot/s for n-channel devices. This structure has inherent advantages such as crystallographicafly single crystalline.     

Submicron gate Si/sub 3/N/sub 4//AlGaN/GaN-metal-insulator-semiconductor heterostructure field-effect transistors

We present the characteristics of a quarter-micron gate metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET) with Si/sub 3/N/sub 4/ film as a gate insulator. A detailed comparison of the MISHFET and an identical geometry HFET shows them to have the same radio frequency (RF) power gain and cut-off frequency, while the MISHFET has much lower gate-leakage currents and higher RF powers at operating frequencies as high as 26 GHz. The MISHFET gate-leakage currents are well below 100 pA at gate bias values from -10 V to +8 V. At zero gate bias, the drain saturation current is about 0.9 A/mm and it increases to 1.2 A/mm at +8 V gate bias. The output RF power of around 6 W/mm at 40 drain bias was found to be frequency independent in the range of 2 to 26 GHz. This power is 3 dB higher than that from HFET of the same geometry. The intrinsic cutoff frequency is /spl sim/63 GHz for both the HFET and the MISHFET. This corresponds to an average effective electron velocity in the MISHFET channel of 9.9/spl times/10/sup 6/ cm/s. The knee voltage and current saturation mechanisms in submicron MISHFETs and heterostructure field-effect transistors (HFET) are also discussed.     

S-band operation of SiC power MESFET with 20 W (4.4 W/mm) output power and 60% PAE

Previous efforts have revealed instabilities in standard SiC MESFET device electrical characteristics, which have been attributed to charged surface states. This work describes the use of an undoped "spacer" layer on top of a SiC MESFET to form a "buried-channel" structure where the active current carrying channel is removed from the surface. By using this approach, the induced surface traps are physically removed from the channel region, such that the depletion depth caused by the unneutralized surface states cannot reach the conductive channel. This results in minimal RF dispersion ("gate lag") and, thus, improved RF performance. Furthermore, the buried-channel approach provides for a relatively broad and uniform transconductance (G/sub m/) with gate bias (V/sub gs/), resulting in higher efficiency MESFETs with improved linearity and lower signal distortion. SiC MESFETs having 4.8-mm gate periphery were fabricated using this buried-channel structure and were measured to have an output power of 21 W (P/sub out//spl sim/4.4 W/mm), 62% power added efficiency, and 10.6 dB power gain at 3 GHz under pulse operation. When operated at continuous wave, similar 4.8-mm gate periphery SiC MESFETs produced 9.2 W output power (P/sub out//spl sim/2 W/mm), 40% PAE, and /spl sim/7 dB associated gain at 3 GHz.     

MOS field effect transistors formed by gate masked ion implantation

MOS enhancement mode field effect transistors with a circular geometry and with drains offset from the gate by distances from 0.1 mil to 0.9 mil were implanted with boron ions to fill in the offset region and thus achieve perfect alignment (i.e., no overlap) between gate and drain. The energies used were 50 to 100 keV and a 4000 Å-thick aluminum gate acted as a mask to prevent ions from penetrating into the channel region. The best junctions were obtained with 100-keV ions, with the sheet resistances being typically 4000 ω/□ for the implanted region. This additional drain resistance was quite small compared to the channel resistance of the devices and so was not objectionable. Ordinary diffused MOSFET's were included on the same wafers for comparison with the ion implanted MOSFET's. It was found that the differences in noise, leakage, and drain breakdown voltage were not serious. The chief advantage of the ion implanted MOSFET is the extremely low feedback capacitance due to the lack of gate-drain overlap, but this advantage is difficult to exploit in a conventional package because of the package capacitance. However, a significant difference was noted in switching characteristics between diffused and ion implanted MOSFET's mounted on TO-18 headers.     

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f_T n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I_d,g_m, Y-parameters, and f _T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NF_min as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz f_T offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R_n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology     

Effects of intermodulation distortion on the performance of a hybrid radio/fiber system employing a self-pulsating laser diode transmitter

A self-pulsating laser is used to generate a multicarrier (five radio frequency (RF) channels) microwave optical signal for use in a hybrid radio/fiber system. The self-pulsation is achieved by external light injection into the laser diode. By varying the RF channel spacing, we have been able to estimate the degradation in system performance due to intermodulation distortion (caused by the nonlinear dynamic response of the laser). The power penalty on the central RF channel is found to be 3.2 dB for operation at the RF band around the laser self-pulsation frequency of 18.5 GHz. We have also characterized the performance of the multicarrier hybrid radio/fiber system in the frequency band corresponding to the inherent relaxation frequency of the laser.     

An All-Digital RF Signal Generator Using High-Speed $DeltaSigma$ Modulators

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm² (0.15 mm² for the active area).     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

耦合式光电振荡器的理论与实验研究

为了研究耦合式光电振荡器,阐述了耦合式光电振荡器的模式选择理论,给出了维持最佳锁模状态的相位匹配条件,分析了影响射频信号相位噪声的因素,进行了基于保偏机制的耦合式光电振荡器的实验研究。采用分别调节光环形腔和光电微波振荡环路中的保偏可变光纤延迟线可改变腔长的方法,获得了腔长与振荡频率的关系。同时,采用鉴频法测量了不同条件下5GHz射频信号的相位噪声,研究了影响射频信号相位噪声的因素。结果表明,耦合式光电振荡器的振荡模式取决于光环形腔的腔长,射频信号相位噪声受到光信号偏振态、相位匹配、环路长度等因素的影响。实验中获得了偏移频率10kHz处相位噪声达到-136dBc/Hz的5GHz射频信号,是目前国内已知的相位噪声最低的耦合式光电振荡器。     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.