Gate oxide integrity dependence on substrate characteristics and SiO2 thickness

Gate oxide integrity (GOI) has been investigated for a wide range of oxide thicknesses, from 5 to 50 nm. Silicon substrates containing voids of number densities along with defect-free (perfect) polished and epitaxial wafers were tested. Oxide reliability was monitored by linear ramped field tests at variable ramp rate and by constant current and field tests using a doped polysilicon gate as the cathode. The field and time parameters characterizing the distributions of each breakdown mode have been extracted by Weibull analysis. In general, more than one mode of breakdown is found in a given sampled substrate type. The average field of the breakdown shifts to higher fields with decreasing oxide thickness. In the void-related mode, a constant countable number of defects for a given substrate type are “activated” at sufficiently high fields independent of oxide thickness. Void-free epi and “perfect” substrates show a single, non-intrinsic breakdown mode. This mode is also found in the void containing materials in the part of their distribution, unaffected by voids.     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

Quality assessment of thin oxides using constant and ramped stress measurements

Two methods are proposed for obtaining extrinsic oxide lifetime data using fast ramped tests. It is shown that the intersection point between the extrinsic and intrinsic branches of a Weibull plot coincides for ramped and constant stress tests. This is the basis of our fast qualification approach, where intrinsic data are obtained by constant voltage stress and extrinsic data are cumulated with a fast ramped test. The correctness of our approaches is supported by constant voltage and exponentially ramped current measurements.     

The time of “guessing” your failure time distribution is over!

Each statistical analysis of reliability data starts with the choice of the underlying distribution of failure times. This choice is of great importance because all conclusions drawn from this analysis will depend on it. Lifetime predictions can vary orders of magnitude depending on the distribution used. Most researchers choose the underlying distribution of failure times rather unfounded: because of “historical” reasons, because everybody uses it,… We developed a method which offers reliability engineers an objective tool for making the distinction between the two most widely used distributions, the lognormal and the Weibull, using a statistical well-founded technique. Essentially, the method comes down to constructing both the lognormal and the Weibull probability plot of the data set under consideration. For each plot, the Pearson's correlation coefficient is calculated. It is shown that the ratio of these two correlation coefficients is a pivotal quantity. Hence, it can serve as a test statistic.     

Ka-band InP high electron mobility transistor monolithic microwave integrated circuit reliability

The reliability of AlInAs/GaInAs high electron mobility transistor (HEMT) monolithic microwave integrated circuits on InP substrates from HRL Labs has been studied with elevated-temperature lifetests on Ka-band LNAs, as well as ramped-voltage tests on individual capacitors. In the lifetests the LNAs were put under normal DC bias, and aging was accelerated by heating to channel temperatures of 190°C and 210°C. Room-temperature characterizations involved DC tests of HEMT parameters as well as 30 GHz measurements of gain, noise figure and phase. Aging caused the noise figure to drop by a few tenths of a dB, and the phase changed by ±10°. The gain dropped gradually by several dB. Taking 1 dB drop in gain as the failure criterion, we find an activation energy of 1.1 eV, and a mean time to failure (MTTF) at an operating channel temperature of 70°C of 7×10⁶ h. In the ramped-voltage tests, 10×10 μm² capacitors were taken to breakdown at two different temperatures, and several ramp rates. This yielded a voltage acceleration factor of γ=36–39 nm/V, and thermal activation energy of 0.11–0.13 eV. Next, ramped voltage tests were conducted on 200×200 μm² capacitors, typical of those in circuits. These were done at 25°C and 3.0 V/s only, and at least 1000 specimens were tested per wafer. The known acceleration factors were used to find the MTTFs at 70°C, with operating biases of 5 or 10 V. For the majority of the population the MTTFs are about 10⁹ h, while only 0.07% of the population has MTTF less than 1×10⁶ h. The combination of results from elevated-temperature lifetests and ramped-voltage capacitor tests indicates excellent reliability for this MMIC technology in terms of known “wearout” failure mechanisms.     

Statistical nature of hard breakdown recovery in high-κ dielectric stacks studied using ramped voltage stress

In replacing the conventional SiO₂ gate dielectric with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the different properties of the new bulk oxide and the interfacial layers at the substrate and gate electrode interface as well. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in resistive random access memory (RRAM). In this study, we explore the stochastic nature of hard breakdown recovery in HfO₂, taking advantage of ramped voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more intense after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring the resistance change trends with temperature.     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

The effect of minimal repairs on economic lot-sizing

This paper examines the problem of lot-sizing in a production facility in the face of machine breakdowns. Failures are dealt with by minimal repairs, until the required lot has been produced, at which point a new cycle is set-up and the machine restored to “as-new” condition. Given the expected duration of a repair, and the duration of a set-up, optimal lot sizes are obtained for Weibull distributed times to failure. Empirical evidence suggests that for an exponential time to failure, the failure process can usually be safely ignored, whereas for machines with a sharply increasingly failure rate, this is not the case.     

Determining constant voltage lifetimes for silicon nitride capacitors in a GaAs IC process by a step stress method

The lifetimes of metal–insulator–metal (MIM) capacitors are predicted from voltage step stress data. Capacitor areas of 400, 5625 and 11,250 μm² are investigated. The reliability of capacitors subjected to a single or triple DC pulse prior to a breakdown voltage ramp test is predicted at use conditions (5 V). The method of maximum likelihood is employed in this analysis. With this approach, it is found that the effect of capacitor area on the linear field acceleration parameter, γ, is not statistically significant. Also, it is demonstrated that either a single or a triple DC pulse seriously reduces both the MTTF and γ. Further, the triple DC pulse can change the failure distribution from lognormal to Weibull. The data are also fitted to the reciprocal field model and the predicted failure times under use conditions are too large to be physically reasonable, favoring the linear field model. A graphical method is suggested for discerning between the lognormal and Weibull distributions.This study makes extensive use of statistical methods. One of our goals in this paper is to make the reliability community aware of these powerful techniques so that they may become more widespread.     

Time-censored ramp tests with stress bound for Weibull lifedistribution

This paper considers ramp tests for Weibull life distribution when there are limitations on test stress and test time. The inverse power law and a cumulative exposure model are assumed. Maximum likelihood estimators of model parameters and their asymptotic covariance matrix are shown. The optimum ramp test plans are given which minimize the asymptotic variance of the ML estimator of a specified quantile of log(life) at design constant stress. The effects of the pre-estimates of design parameters are studied     

Implications of a localised defect model for wafer level reliability measurements of thin dielectrics

In this paper a simple model of an oxide defect as a region of localised oxide thinning is used to explore the relationship between the most commonly used measurements of dielectric reliability. For each measurement it shows how the measured parameters depend on the area and effective thickness of the defect. The work shows that in constant voltage and ramped voltage stress the area and thickness of the defect may be easily separated in the measured parameters. However, in constant current and ramped current measurements all measured parameters are dependent on both area and thickness which makes the extraction of area and thickness more difficult. It is shown that, in order to be able to project from one measurement to any other, the defect area and thickness must be determined. In particular, if projections of charge to breakdown are required then the use of a model which only includes defect thinning as proposed by Lee et al, [1], is not sufficient.     

A flexible bathtub hazard model for non-repairable systems with uncensored data

This research effort has developed a mathematical model for bathtub shaped hazards (failure rates) for operating systems with uncensored data. The model will be used to predict the reliability of systems with such hazards. Early in the life-time of a system, there may be a relatively large number of failures due to initial weaknesses or defects in materials and manufacturing processes. This period is called the “infant mortality” period. During the middle period of an operating system fewer failures occur and are caused when the environmental stresses exceed the design strength of the system. It is difficult to predict the environmental stress amplitudes or the system strengths as deterministic functions of time, thus the middle-life failures are often called “random failures.” As the system ages, it deterioates and more failures occur. This region of failure is called the “wearout” period. Graphing these failure rates simultaneously will result in a bathtub shaped curve. The model developed for this bathtub pattern of failure takes into account all three failure regions simultaneously. The model has been validated for accuracy by using Halley's mortality table and is used to predict the reliability with both least squares and maximum likelihood estimators.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Tunnel barrier properties of stressed ferromagnetic tunneljunctions

The oxide breakdown properties of ultra-thin (-1 nm) naturally oxidised Al₂O₃ tunnel barriers in magnetic tunnel junctions were studied using ramped and constant stress experiments. During stress measurements at 1.35 V, a fast breakdown of the junction was observed. The time-to-breakdown is evaluated using Weibull statistics, as commonly utilised in SiO₂ reliability studies     

Weibull characteristics of n-MOSFET's with ultrathin gate oxides under FN stress and lifetime prediction

Subthreshold gate voltage shift ΔV_gw of n-MOSFET's with different oxide thicknesses aging at various stress conditions was statisticalized using Weibull distribution. Based on the statistical results, an empirical expression for the relationship between average lifetime and acceleration field was developed, and lifetime predictions were made. Results show that the shape factors (β) of intrinsic failure of the devices with 5.0, 7.0, and 9.0 nm gate oxides under 27 and 105 °C are the same, namely, the mechanisms of the intrinsic failure are the same under low and high temperatures. The proportion of the extrinsic failure increases with temperature increasing. A lifetime prediction method was developed based on the exponential relationship between lifetime and acceleration field. This method can be applied to predict the lifetime of n-MOSFET's with ultrathin gate oxides under FN stress.     

A general Weibull model for reliability analysis under different failure Criteria-application on anisotropic conductive adhesive joining technology

In this paper, a generic four-parameter model has been developed and applied to the anisotropic conductive adhesive (ACA) flip-chip joining technology for electronics packaging applications. The model can also be used to predict any minimum failure cycles if the maximum acceptable failure criterion (in this case, a preset electrical resistance value) is set. The original reliability testing from which the test data was obtained was carried out on flip-chip anisotropically conductive adhesive joints on an FR-4 substrate. In the study, nine types of ACA and one nonconductive film (NCF) were used. In total, nearly 1000 single joints were subjected to reliability tests in terms of temperature cycling between -40/spl deg/C and 125/spl deg/C with a dwell time of 15 min and a ramp rate of 110/spl deg/C/min. The reliability was characterized by single contact resistance measured using the four-probe method during temperature cycling testing up to 3000 cycles. A single Weibull model is used for two failure definitions defined as larger than 50 m/spl Omega/ and larger than 100 m/spl Omega/ respectively using the in situ electrical resistance measurement technique. The failure criteria are incorporated into this Weibull model. This paper shows the flexibility and usefulness of Weibull distribution in this type of applications.     

Robustness of the exponential sequential probability ratio test (SPRT) when Weibull distributed failures are transformed using a “known” shape parameter

Assumptions accompanying exponential failure models are often not met in the life-testing of many products. Several authors have suggested sequential life testing techniques that transform Weibull failure times to an exponential density using the “known” Weibull shape parameter. In practice, this parameter is never known and must be estimated. This paper demonstrates that procedures based on this transformation are extremely sensitive to mis-specification of the shape parameter. Furthermore, it is doubtful that the shape parameter may be estimated with enough precision to successfully implement these procedures. Using a Weibull sequential test without the transformation yields better results; however, sensitivity analysis to shape parameter mis-specification is recommended before any specific test is implemented.     

A new reliability prediction model for telecommunication hardware

An analysis of measured field failure rates of printed circuit boards has been performed. The “part count” method currently used for reliability predictions was evaluated. A new model for electronic reliability prediction has been proposed. It uses statistics from board and system tests performed at the production plant and the number of conductive layers on the board. The report shows that there is a correlation between production test statistics and field performance, for high-volume boards. The proposed model shows that a high production test yield indicates high field reliability. This means that if actual production test results are poor, actions can be taken to improve reliability before numerous boards are delivered to customers.     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring     

Chip Scale Package (CSP) solder joint reliability and modeling

A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in Chip Scale Packages (CSP) mounted on Printed Circuit Boards (PCB). The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2-D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. A viscoelastic constitutive model was used for molding compound. Finite element models, incorporating the viscoplastic flow and evolution equations for solder and the viscoelastic equations for molding compound, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless Lead-on-Chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints while a dwell time in excess of 10 min per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between the experiment and the model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated and the primary factors affecting solder fatique life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.