Silicon-on-insulator bipolar transistors

Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.     

An SOI voltage-controlled bipolar-MOS device

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.     

Accurate delay models for digital BiCMOS

A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection leading to BJT β roll-off, base pushout leading to BJT f_T roll-off, short-channel behavior of the MOS drain current, and parasitic capacitances at the base and output. Based on the transient analysis, a piecewise delay expression is derived that shows excellent agreement with measured gate delay and with SPICE simulated delay. The comparisons are made for a wide range of circuit parameters in the gate, namely, MOSFET/BJT size, load capacitance, and supply voltage for both 1- and 0.6-μm BiCMOS technologies. The model is used to optimally size gates, and to determine circuit and device design guidelines to minimize the delay degradation at reduced supply     

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm²/V.s and drain breakdown voltage exceeding 15 V.     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Lateral p-n-p bipolar junction transistors (BJTs) fabricated using a bulk 0.25 μm CMOS technology are presented. The devices are structurally the same as p-MOSFETs in which the gate and the n-well are internally connected to form the base. The p-n-p BJT has an adjustable current gain which can be higher than 1000 and its peak cutoff frequency is 3.7 GHz. Since the lateral p-n-p BJT is fully process compatible with submicrometer CMOS and/or BiCMOS technologies, extension to a BiCMOS and/or complementary BiCMOS process is readily achieved     

A 150-V multiple up-drain VDMOS, CMOS, and bipolar process in`direct-bonded' silicon on insulator on silicon

Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15-μm thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2-μm gates, and bipolar transistors. The up-drain VDMOS transistors with 2-Ω-mm ² specific on-resistance allow multiple isolated outputs, so high-voltage push-pull drivers can be fabricated in a single chip. The bipolar transistors are comparable to those of a 60-V standard process with vertical n-p-n and lateral p-n-p current gains of 80     

Potential design and transport property of 0.1-μm MOSFET withasymmetric channel profile

This paper describes potential design and transport property of a 0.1-μm n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-μm device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-μm n-MOSFET with asymmetric channel profile     

Lateral HVIC with 1200-V bipolar and field-effect devices

The 1200-V blocking capability of lateral high-voltage devices has been achieved through theoretical and experimental investigation. The feasibility of a 1200-V lateral n-p-n bipolar junction transistor, p-n diode, and lateral DMOSFET has been demonstrated for the first time. The on-resistance of the 1200-V DMOSFET is 4 times less than its 1200-V n-p-n BJT counterpart. The major contribution to high BJT on-resistance comes from the series JFET pinch resistance.     

一种考虑复合电流的SiC LBJT行为模型改进

介绍了一种考虑基区SiC/SiO₂界面处复合电流的SiC LBJT改进模型。分析了横向碳化硅双极结型晶体管与其垂直结构之间的区别,将横向BJT的外延层和半绝缘机构等效为衬底电容。再引入一个平行于SiC BJT基极结的附加二极管来描述复合电流,以垂直SiC BJT的SGP模型为基础建立SiC LBJT行为模型。校准了LBJT模型的基区渡越时间,模型与实际器件的开关特性接近吻合。相较于未考虑复合电流的LBJT模型,改进后的模型输出特性曲线与实测数据精度误差较小。该模型可以较精确地描述受复合电流影响的LBJT器件行为。     

Parasitic bipolar gain reduction and the optimization of 0.25-μmpartially depleted SOI MOSFETs

An in-depth analysis of the role of parasitic bipolar gain reduction in 0.25-μm partially depleted SOI MOSFETs is presented, considering both dc characteristics as well as circuit operation. The effect of channel doping, silicide proximity, and germanium implantation on the lateral bipolar gain are characterized for optimal performance and manufacturability. Channel doping has the expected impact on bipolar gain. Silicide proximity is shown also to have a large impact. Germanium implantation into the source/drain regions reduces the lateral bipolar gain due to the introduction of defects that act as recombination centers in the source, reducing emitter efficiency. Further, germanium implantation serves to finely control the silicidation process, leading to good manufacturing control of the lateral silicide encroachment. Analysis of MOSFET dc I-V characteristics shows that threshold voltages for SOI have to be set only 30-50 mV higher for comparable dc off current to bulk CMOS. Finally, the impact of bipolar gain on floating-body-induced hysteretic effects and on alpha-particle-induced SRAM soft error rates are described     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel     

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.     

Demonstration and properties of a planar heterojunction bipolartransistor with lateral current flow

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 μm. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-μm stripe     

Near-ideal I-V characteristics of GaInP/GaAsheterojunction bipolar transistors

GaInP/GaAs heterojunction bipolar transistors (HBTs) have been fabricated and these devices exhibit near-ideal I-V characteristics with very small magnitudes of the base-emitter junction space-charge recombination current. Measured current gains in both 6-μm×6-μm and 100-μm×100-μm devices remain constant for five decades of collector current and are greater than unity at ultrasmall current densities on the order of 1×10^-6 A/cm². For the 6-μm×6-μm device, the current gain reaches a high value of 190 at higher current levels. These device characteristics are also compared to published data of an abrupt AlGaAs/GaAs HBT having a base layer with similar doping level and thickness     

A new 0.25-μm recessed-channel MOSFET with selectivelyhalo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V_T lowering effect and the lateral electric field at the drain. A 0.25-μm GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V_D=V _G=3.3 V, 1 V higher BV_DSS, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions     

Low-voltage transient bipolar effect induced by dynamicfloating-body charging in scaled PD/SOI MOSFETs

An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 μm SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems     

Small geometry depleted base bipolar transistors (BSIT)—VLSI devices?

An essential characteristic of devices which are viable candidates for VLSI circuits is that they must have electrical characteristics which can tolerate process variations. Conventional bipolar junction transistors (BJT) are well known to be limited by punchthrough when vertical basewidths axe decreased; these devices are, however, relatively tolerant of linewidth variations. The depleted base bipolar transistor represents a limiting case when the metallurgical basewidth is allowed to shrink to zero. Such devices, also called bipolar static induction transistors (BSIT), have been proposed as candidates for VLSI logic circuits. This paper describes the basic device physics of depleted base transistors and presents experimental verification of the theoretical modeling. The two essential conclusions that are drawn are that such devices can only achieve performance (in terms of transconductance) comparable to BJT's when an electrical p-type base exists (n-p-n device) and secondly, that BSIT's have characteristics which are extremely sensitive to process variations (linewidths, junction depths, and doping profiles). As a consequence, we conclude that while pure bipolar transistors may play an important role in VLSI circuits, depleted base structures such as the BSlT, are unlikely candidates for such applications.     

High-performance, graded-base AlGaAs/InGaAs collector-upheterojunction bipolar transistors using a novel selective area regrowthprocess

Graded-base AlGaAs/InGaAs collector-up heterojunction bipolar transistors (C-up HBTs) were successfully fabricated using a novel selective area regrowth process to reduce the base resistance and their dc and microwave performances were evaluated. The base is compositionally graded to provide a quasi-built-in field which decreases the base transit time for high-frequency response and increases the base transport factor at low-temperature operation. A unity-gain cutoff frequency f_T=55 GHz and a maximum frequency of oscillation f _MAX=74 GHz for the C-up n-p-n HBT, and an f_T=48 GHz and an f_MAX= 39 GHz for the C-up p-n-p HBT were obtained for devices with a 5-μm×10-μm collector area. The nonself-aligned C-up HBT's reported here show great promise for future high-speed C-up complementary bipolar IC's     

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.