High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Lateral p-n-p bipolar junction transistors (BJTs) fabricated using a bulk 0.25 μm CMOS technology are presented. The devices are structurally the same as p-MOSFETs in which the gate and the n-well are internally connected to form the base. The p-n-p BJT has an adjustable current gain which can be higher than 1000 and its peak cutoff frequency is 3.7 GHz. Since the lateral p-n-p BJT is fully process compatible with submicrometer CMOS and/or BiCMOS technologies, extension to a BiCMOS and/or complementary BiCMOS process is readily achieved     

Thin-film lateral bipolar transistor in silicon-on-sapphire structure

Heteroepitaxial films of silicon-on-sapphire were used to fabricate lateral bipolar n-p-n transistors. The devices have a common-base direct-current amplification factor of 0.9 and a maximum frequency of oscillation of 2.4 GHz. As a result of the vertical p-n-junction arrangement, small junction areas are possible, e.g. 1×10?6cm2, which yield depletion-layer capacitances of 0.02?0.05 pF.     

High-gain 9.25 GHz silicon bipolar transistor power amplifier

A four-stage silicon bipolar transistor power amplifier operating at centre frequency 9.25 GHz is reported. The amplifier has output power exceeding 1.0 W over an instantaneous bandwidth of approximately 800 MHz. The power-added efficiency of the amplifier is measured to be better than 18%.     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

High-gain InGaAlAs/InGaAs heterojunction bipolar transistors andphototransistors

The characteristics of InGaAlAs/InGaAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy are described. A current gain of 15600 at a current density of ~10⁴ A/cm² and an emitter-base heterojunction ideality factor of 1.02 were measured. Appropriately designed InGaAlAs/InGaAs HBTs, when operated as phototransistors, also had high gains. A current gain of 1000 for a collector current of only 10 μA was obtained for phototransistors. Such high gains are due to low recombination currents as a consequence of the good crystalline quality of the InGaAlAs bulk and InGaAlAs/InGaAs interface     

Investigation of MOSFET operation in bipolar mode

The work is concerned with the properties of conventional MOSFET in bipolar mode of operation. It is shown that the base current can provide useful information about interface trap density at the Si–SiO₂ interface. The new device characteristics are found promising for use in low-voltage low-power logic circuits.     

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

Blocking and desensitization in bipolar and MOSFET differentialamplifiers

Blocking and desensitization are among the nonlinear effects that result when bipolar and MOSFET differential amplifiers are operating in a multisignal electromagnetic interference (EMI) environment. When a weak desired signal is processed along with a strong undesired interferer signal, the weak signal may experience a reduced gain; that is, desensitization. If the amplitude of the undesired signal is sufficiently large, the gain of the desired signal may drop to zero; that is, blocking. Using a Fourier-series model for the differential input-voltage/output-current characteristics, closed-form expressions for predicting the desensitization in bipolar and MOSFET differential amplifiers are presented. These expressions are valid over a wide range of desired and blocking interfering signals amplitudes     

Periodically doped MOSFET structure

A novel SOI MOSFET structure is presented that is designed to be operated at 4–600 K and is expected to provide an improvement in performance and reliability. It essentially employs high doping of peripheral source/drain regions and longitudinally periodic doping of the gates and channel.     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

High-gain GaInP/GaAs heterojunction phototransistor utilising guard-ring structure

GaInP/GaAs heterojunction phototransistors with an emitter guard-ring contact are fabricated. The gain and speed of response of a device is significantly improved by the application of bias to the guard-ring, indicating that the recombination current is surface-dominated and that the quality of the GaInP/GaAs heterojunction interface is high.<>     

A column-base InP lateral bipolar transistor

An InP lateral bipolar transistor has been successfully fabricated on a semi-insulating substrate by implanting Si⁺ as the emitter and collector contacts and Mg⁺ as the column base. An array of 33 1-μm-diameter columns with 1-μm separation between each was formed between the emitter-collector spacing of 3 μm. A current gain of 290 was obtained at 77 K; it was over 12 at room temperature     

Highly linear and low noise differential bipolar MOSFET down-converter in CMOS process

A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 μm CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.     

Performance of a CMOS compatible lateral bipolar photodetector onSOI substrate

The performance of a photodetector fabricated using a standard CMOS process on SOI substrate has been studied. The photodetector is basically a floating gate SOI NMOSFET operating in the lateral bipolar mode. The depletion region induced by the floating gate separates the optically generated electron-hole pairs in the direction perpendicular to the current. This results in an extra current amplification beyond that of a normal lateral bipolar transistor. A high responsivity of 289 A/W has been measured with an operating voltage as low as 0.1 V. The impacts of technology scaling on the performance of the photodetector are also studied     

A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact

A novel lateral bipolar transistor structure in silicon-on-insulator (SOI) is presented. The structure allows for a minimum geometry base width yet still provides for a metal contact to the entire base region. Fabricated transistors exhibit a base resistance of less than 20 Ω.     

Effect of mobile charge on hot-carrier degradation in lateral diffused MOSFET

Hot carrier-induced device degradation in n-type lateral diffused MOSFETs with mobile charges in gate oxide has been studied. Abnormal decrease-then-increase in V/sub th/ during hot-carrier stress was observed. The decrease was found to be caused by movement of mobile charges while the increase was the normally observed hot-electron degradation. The hot-electron degradation was drastically accelerated with the presence of mobile charges and easily recovered after baking or negative gate bias. The magnitude of degradation linearly increases with mobile charge density. The acceptable limits of mobile charge density have been estimated. The observed behaviors are very similar to positive charging processes found in other n-MOSFETs that were attributed to hot-hole effects, suggesting mobile charge induced degradation must be carefully excluded in hot-hole injection studies.     

Physical modeling of lateral scaling in bipolar transistors

The dependence of important transistor characteristics, such as transit frequency, on emitter width and length is modeled on a physical basis. Closed-form explicit analytical equations are derived for modeling the emitter size dependence of the low-current minority charge and transit time, the critical current indicating the onset of high injection in the collector, and the stored minority charge in the collector at high injection. These equations are suited for application in various compact transistor models such as the SPICE Gummel-Poon model (SGPM) as well as the advanced models HICUM and MEXTRAM. As demonstrated by two- and three-dimensional device simulation and measurements, combination of the derived equations with HICUM results in accurate prediction of the characteristics of transistors with variable emitter length and width. As a consequence, the new model makes the conventional transistor library unnecessary and offers bipolar circuit designers the flexibility to use the transistor size that fits the application best     

Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J_B) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J_B ^1.8 for J_B<0.4 μA/μm², which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (J_B>0.4 μm²), the noise bias dependence shifts to J_B ^1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region     

A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact

A novel trench lateral power MOSFET with a trench bottom source contact (TLPM/S) is proposed, fabricated, characterized, and compared with the equivalent TLPM with a trench bottom drain contact (TLPM/D). The TLPM/S is formed along the sidewalls of the trenches so as to reduce the device pitch and realize very small on-resistance per unit area. A total of eight masks are used for fabricating the device. Since the gate electrode and the trench bottom source contact are formed by self-aligning to the trench sidewalls, the device pitch is reduced. Using a line width of 0.6 /spl mu/m, the fabricated TLPM/S, whose device pitch is 3.0 /spl mu/m, exhibits a specific on-resistance of 60 m/spl Omega/-mm/sup 2/ for a breakdown voltage of 73 V, which is close to the estimated silicon limit for this voltage class of devices. Due to reduced Miller capacitance, the TLPM/S exhibits excellent switching performance, and is approximately 50% faster than the equivalent TLPM/D.     

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.