Good High-Temperature Stability of TiN/ Al2O3/WN/TiN Capacitors

For the first time, good thermal stability up to an annealing temperature of 1000degC has been demonstrated for a new TiN/Al₂O₃/WN/TiN capacitor structure. Good electrical performance has been achieved for the proposed layer structure, including a high dielectric constant of ~ 10, low leakage current of 1.2times10^-7 A/cm² at 1 V, and excellent reliability. A thin WN layer was incorporated into the metal-insulator-metal capacitor between the bottom TiN electrode and the Al₂O₃ dielectric suppressing of interfacial-layer formation at Al₂ O₃/TiN interfaces and resulting in a smoother Al₂O₃/TiN interface. This new layer structure is very attractive for deep-trench capacitor applications in DRAM technologies beyond 50 nm.     

High-Temperature Stable HfLaON p-MOSFETs With High-Work-Function Ir3Si Gate

We report a novel 1000 degC stable HfLaON p-MOSFET with Ir₃ Si gate. Low leakage current of 1.8times10^-5 A/cm² at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm²/Vmiddots are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degC rapid thermal annealing is fully compatible to current very large scale integration fabrication lines     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

Novel Integration of Metal–Insulator–Metal (MIM) Capacitors Comprising Perovskite-type Dielectric and Cu Bottom Electrode on Low-Temperature Packaging Substrates

In this letter, a novel integration scheme, for metal-insulator-metal capacitors comprising perovskite-type dielectrics and Cu-based bottom electrodes, has been demonstrated on low-temperature FR4 packaging substrates. Cu oxidation during dielectric deposition and postannealing is completely avoided by a dielectric-first process flow with Ti as oxygen-getter. By using evaporated barium strontium titanate as capacitor dielectric, a maximum capacitance density (~1250 nF/cm² at 100 kHz) and moderate leakage current (< 4 times 10^-5 A/cm² at 2 V) have been achieved with rapid thermal annealing at 700degC. Higher temperature leads to dielectric degradation. Combined with advanced deposition techniques, this integration scheme enables realization of high-performance embedded capacitors that can be integrated with printed circuit board technology.     

Low Subthreshold Swing HfLaO/Pentacene Organic Thin-Film Transistors

We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of -1.3 V, and a field-effect mobility of 0.71cm²/ Vldrs . This occurred along with an ON-OFF state drive current ratio of 1.0 times 10⁵, when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm² that is given by the HfLaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 times 10^-7 at 2 V.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

Improved High-Temperature Leakage in High-Density MIM Capacitors by Using a TiLaO Dielectric and an Ir Electrode

We have fabricated high-kappa TaN/Ir/TiLaO/TaN metal-insulator-metal capacitors. A low leakage current of 6.6 times 10^-7 A/cm² was obtained at 125degC for 24-fF/mum2 density capacitors. The excellent device performance is due to the combined effects of the high-kappa TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

High-Performance Metal–Insulator–Metal Capacitors Using Amorphous BaSm2Ti4O12 Thin Film

The dielectric properties of the amorphous BaSm₂Ti₄O₁₂ (BSmT) film with various thicknesses were investigated to evaluate its potential use as a metal-insulator-metal (MIM) capacitor. An amorphous 35-nm-thick BSmT film grown at 300 degC exhibited a high capacitance density of 9.9 fF/mum² at 100 kHz and a low leakage current density of 1.790 nA/cm² at 1 V. The quadratic and linear voltage coefficients of capacitance of the film were 599 ppm/V² and -81 ppm/V at 100 kHz, respectively. The temperature coefficient of capacitance of the film was also low about 236 ppm/degC at 100 kHz. These results confirmed the suitability of the amorphous BSmT film as a high-performance MIM capacitor     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

High-Temperature Leakage Improvement in Metal–Insulator–Metal Capacitors by Work–Function Tuning

Using low-cost and high work-function Ni, a low leakage current of 5times10^-6 A/cm² at 125 degC is obtained in a high 25-fF/mum²-density SrTiO₃ metal-insulator-metal (MIM) capacitor processed at 400 degC. This is approximately two orders of magnitude better than the same device using a TaN electrode, with added advantages of improved voltage and temperature coefficients of capacitance. This work-function tuning method also has merit for achieving both low thermal leakage and high overall kappa value beyond previous laminate structure     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Dark-Current Suppression in Metal–Germanium–Metal Photodetectors Through Dopant-Segregation in NiGe—Schottky Barrier

We demonstrate, for the first time, the application of dopant-segregation (DS) technique in metal-germanium- metal photodetectors for dark-current suppression and high-speed performance. Low defect density and surface smooth epi-Ge (~300 nm) layer was selectively grown on patterned Si substrate using two-step epi-growth at 400degC/600degC combined with a thin (~10 nm) low-temperature Si/Si_0.8 Ge_0.2 buffer layer. NiGe with DS effectively modulates the Schottky barrier height and suppresses dark current to ~10 ^-7 A at -1 V bias (width/spacing: 30/2.5 mum). Under normal incidence illumination at 1.55 mum, the devices show photoresponsivity of 0.12 A/W. The 3 dB bandwidth under - 1 V bias is up to 6 GHz.     

Oxide-confined 850 nm VCSELs operating at bit rates up to 40 Gbit/s

Oxide-confined 850 nm vertical-cavity surface-emitting lasers operating at 40 Gbit/s at current densities ~10 kA/cm² are realised. The deconvoluted rise time of the device is below 10 ps and remains hardly temperature sensitive up to 100degC.     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made     

Enhancing the Near-Infrared Spectral Response of Silicon Optoelectronic Devices via Up-Conversion

A silicon-based optoelectronic device that exhibits an enhanced response to subbandgap light is described. The device structure consists of a bifacial silicon solar cell with an up- converting (UC) layer attached to the rear. Erbium-doped sodium yttrium fluoride (NaY_0.8F₄ : Er_0.2 ³⁺) phosphors are the optically active centers responsible for the UC luminescence. The unoptimized device is demonstrated to respond effectively to wavelengths (lambda) in the range of 1480-1580 nm with an external quantum efficiency (EQE) of 3.4% occurring at 1523 nm at an illumination intensity of 2.4 W/cm² (EQE = 1.4 times 10^-2 cm²/W). An analysis of the optical losses reveals that the luminescence quantum efficiency (LQE) of the device is 16.7% at 2.4 W/cm² of 1523-nm excitation (LQE = 7.0 times 10^-2 cm²/W), while further potential device improvements indicate that an EQE of 14.0% (5.8 times 10^-2 cm²/W) could be realistically achieved.     

Saturation of 1047- and 1064-nm Absorption in Cr4+:YAG Crystals

To investigate the physical mechanism of the saturation process in Cr⁴⁺:YAG crystals we solved the three coupled rate equations which describe the saturable absorber. We experimentally verified this model using two lasers with nanosecond pulses and continuous-wave radiation. We used crystalline and ceramic Cr⁴⁺-doped YAG saturable absorbers with various initial transmissions. The ratio between the ground and the excited-state absorption cross section at 1064 nm was measured to be between 3.8 plusmn 0.2 and 4.7 plusmn 0.2 for crystalline and 3.6 plusmn 0.1 for ceramic Cr⁴⁺:YAG. The ratio between the above named cross sections at 1047 nm was found to be 6.2 plusmn 0.2 for both crystalline and ceramic Cr⁴⁺:YAG. With these results the ground-state and the excited-state absorption cross sections at 1047 nm were calculated to be (9.55plusmn0.01)times10^-19 cm² and (1.54plusmn0.03)times10^-19 cm², respectively     

Fabrication of planar optical waveguides in LiB3O5 by 2 MeV He+ ion implantation

The fabrication of planar optical waveguides in LiB₃O ₅ is discussed. Using 2-MeV ⁴He⁺ implantation with a dose of 1.5×10¹⁶ ions/cm² at 300 K, the refractive indexes of a 0.2-μm-thick layer 5.1 μm below the crystal surface are reduced to form optical barrier guides. For this ion dose the maximum change from the bulk values of refractive index at a wavelength of 0.488 μm are 1.5%, 5.25%, and 4% for n_x, n_y, and n_z, respectively. The refractive indexes of the guiding region change by less than 0.02% from the bulk values. The dose dependence of the optical barrier height has been measured. A threshold ion dose of about 0.75×10¹⁶ ions/cm² is required to form a refractive index barrier and ion doses higher than about 2.5×10¹⁶ ions/cm². saturate the refractive index decrease. Waveguide propagation losses for annealed single energy implants of dose 1.5×10¹⁶ ions/cm² are dominated by tunneling and are estimated to be ~8.9 dB/cm for the z-cut waveguides used. Multiple energy implants broaden the optical barrier, and losses of <4 dB/cm have been observed