利用流水并行比较法的模数转换器

提出了一种新型模数转换方法--流水并行式模数转换法，并给出了相应的ADC实验结果。还介绍了流水并行式ADC的电路设计和具体实现的要点。     

并行输出10位模数转换器TLC1551的原理与应用

TLC1551是美国TI公司生产的10位并行输出模数转换器，该器件转换速度快，传输数据方便，应用电路简单。文中介绍了TLC1551的管脚功能、电气特性、工作原理和时序、应用电路及模数转换的单片机基本程序，给出了可供数据采集的工程参考。     

非易失性数控电位器在温度测量中的应用

文章介绍了一种利用非易失性数控电位器Ｘ９３１２构成的温度测量电路的原理，该电路作为一种记数式模数转换电路也可用于其它应用场合。     

一种利用流水并行比较法的A／D转换器

提出和验证了一种利用新型流水并行式模数转换法的A／D转换器（ADC）。在达到并行比较式ADC相同转换时间tc的前提下，流水并行式ADC的tc和n函数关系等同于并行比较式ADC，而其m和n函数关系优于并行比较式ADC，并且比流水式ADC易于实现。介绍了流水并行式ADC的电路设计和具体实现的要点，给出了相应的ADC易于实现。介绍了流水并行式ADC的电路设计和具体实现的要点，给出了相应的ADC实验结果和时序。     

利用89C2051实现模数转换的一种方法

本文介绍一种新的实现模数转换的方法。此种方法不需专用模数转换芯片,利用89C2051自身的一个模拟比较器就可以很方便地实现模数转换。降低了开发成本并减少了电路体积,是一种很实用的模数转换方法,使用于袖珍仪器的场合。     

高速光子模数转换技术及其集成化研究进展（特邀）

光子模数转换技术是克服传统电子模数转换技术在采样速率、输入带宽、时钟抖动和比较器模糊等局限性的有效手段。光子模数转换技术为超宽带雷达、超高速示波器、大容量光通信等前沿应用的高速率、大带宽、高精度接收提供了有效解决方案。文章首先简要介绍了光子模数转换技术的技术途径分类及对比,然后重点介绍作者所在课题组围绕并行解复用光子模数转换系统开展的理论研究与应用研究工作。此外,分析了集成光子模数转换系统现状并展望了其未来发展思路和关键挑战。最后对全文进行了总结。     

高速高精度ADC系统分析

对于提高模数转换系统的速度和性能,并使用相对低速的电路来实现高速采样的模数转换系统来说,时间交叉采样模数转换系统是一种非常有效的方法。本文介绍了时间交叉采样法的基本原理和实现方法,并对系统中各通道间的失配对整个系统性能的影响做出了分析,给出了仿真图形。     

基于AVR和CPLD的高速数据采集系统

为了提高数据采集卡的速度,同时降低成本,设计一种并行数据采集系统,要求并行采集速度大于10 Mb/s.整个系统由AVR与CPLD控制实现,通过MAX1308完成模数转换,并设计搭建了其外围电路.采用12路数据存储模式存储高速采集的数据.实验依据存储要求搭建硬件电路并调试,示波器显示的波形结果8组脉冲序列完全对齐,没有出现时序混乱,同时并行处理过程中不相互影响,实现了低成本高速多路采集的设计要求.     

基于SIM900A的智能心电监护系统客户端

设计了一种智能心电监护系统客户端,设置于患者处的终端设备通过无线网络连接和因特网与主机服务器通信连接。终端设备包括采样电路、滤波电路、模数转换电路、微处理器、存储器、人机接口和通讯接口,所述采样电路与所述滤波电路连接;所述滤波电路与所述模数转换电路连接。该客户端能够及时将异常心电数据发送给智能心电监护系统,对患者进行实时的监控,捕捉发现异常的信息,提供给患者,从而实现早发现早治疗的目的。     

新型超宽带探地雷达数字采样接收机设计

基于探地雷达应用,结合等效时间采样技术和实时采样技术的优点,提出了一种新的超宽带等效数字采样技术。该采样技术不需要采用集成模数转换(A/D),而是通过对模拟信号进行1比特并行时间交替采样和均匀量化来实现模数转换的功能。基于该技术思想,利用一片现场可编程门阵列(FPGA)研制出具有等效4.096GHz采样率、7位精度模数转换功能的超带宽探地雷达数字采样接收机。电路结构紧凑,功耗低于1.5W.实测结果表明:该接收机的模拟带宽达500MHz,具有很低的量化噪声,能很好的重构输入信号。同时,该接收机具有很好的性能,能满足超宽带探地雷达的要求。     

基于C8051F的模数转换及其在直流电机驱动系统中的应用

介绍了由Silicon Labs公司C8051F001/2/5/6/7系列单片机自身具有的12位精度SAR ADC实现A/D转换的方法,此方法无需任何接口电路,无需专用模拟转换器,降低了开发成本,减小了电路体积,可广泛应用于各种便携式装置,还介绍了基于A/D系统的单极性直流电动机的驱动方法.     

一种基于流水逐次逼近比较方式的模／数转换器

提出了一种新型模数转换方法——流水逐次逼近比较式模数转换法,并给出了相应的实验结果。在达到逐次逼近比较A/D转换器的相同转换时间tc的前提下,流水逐次逼近比较式A/D转换器的m和n函数关系等同于逐次逼近比较A/D转换器,而其tc和n的函数关系优于逐次逼近比较A/D转换器,并且比较流水式A/D转换器易于实现。     

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ADC that requires a light calibration logic (area: 0.123 mm², power: 72 mW) or a faster, tinier and even lower power ADC (area: 0.21 mm², power: 25 mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225 MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420 MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7 dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.     

基于输出迭代法的A/D转换器测试数据分析

介绍了一种将模拟/数字转换器(ADC)的采样输出按照正弦输入信号的周期进行迭代的数据处理方法,可以评估输入噪声和时钟抖动对动态性能测试结果的影响。同时,通过分析迭代后的信号波形,可以发现高频输入信号在ADC转换过程中存在的畸变、非单调、失码、跳码、失真等现象,而这些现象很难从输出数据中直接观察到。这种分析对ADC的设计具有重要的指导意义。实验结果表明,这种方法是实用有效的。     

Ultra-wideband analog-to-digital conversion via signal expansion

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.     

An all-digital analog-to-digital converter with 12-/spl mu/V/LSB using moving-average filtering

A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure is a completely digital circuit including a ring-delay-line with delay units (DUs), along with a frequency counter, latch, and encoder. The operating principles are: (1) the delay time of the DU is modulated by the analog-to-digital (A/D) conversion voltage and (2) the delay pulse passes through a number of DUs within a sampling (= integration) time and the number of DUs through which the delay pulse passes is output as conversion data. Compact size and high resolution were realized with an ADC having a circuit area of 0.45 mm/sup 2/ (0.8-/spl mu/m CMOS) and a resolution of 12 /spl mu/V (10 kS/s). Its nonlinearity is /spl plusmn/0.1% FS per 200-mV span (1.8-2.0 V), for 14-b resolution. Sample holds are unnecessary and a low-pass filter function removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion. Also, both this ADC can be shrunk and operated at low voltages, so it is an ideal means to lower the cost and power consumption. Drift errors can be easily compensated for by digital processing.     

基于FPGA的高速采样电路设计与测试

提出利用Xilinx公司新一代现场可编程门阵列(FPGA)-Virtex5芯片对超高速模数转换器ADC08D1500的控制和数据处理方法.实现了ADC08D1500高速稳定的工作和高速被采信号的降速处理,以解决工程中系统采样速率和采样精度问题.详细介绍了布线制板需要注意的特殊问题,最后给出了通过chipscope软件得到的被采信号图,结果显示ADC08D1500性能出色具有高于6.5bit有效位数.设计在工程实践中已经得到使用,并取得了良好的效果.     

一种基于映射结构的新颖A/D转换器的研究和仿真

本文研究了一种新型的混沌A/D转换器,这是一种基于非线性映射结构的非流水式ADC,并提出基于开关电容的ADC电路设计.理论分析和实验仿真表明本文所提出的A/D转换器克服了流水结构A/D变换器多级之间的增益匹配和每级中A/D和D/A变换之间的匹配等主要影响精度的设计问题,具有对噪声干扰不敏感等特性,降低了对部分元器件的精度等要求,可能为高速高精度A/D转换器的设计提供一种新的途经.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.     

Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system

To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system.