Silicide application on gated single-crystal, polycrystalline andamorphous silicon FEAs. I. Mo silicide

In order to improve both the level and the stability of electron field emission, the tip surface of silicon field emitters have been coated with a molybdenum layer of thickness 25 nm through the gate opening and annealed rapidly at 1000°C in inert gas ambient. The gate voltages of single-crystal silicon (c-Si), polycrystalline silicon (poly-Si) and amorphous silicon (a-Si) field emitter arrays (FEAs) required to obtain anode current of 10 nA per tip are 90 V, 69 V, and 84 V, respectively. In the case of the silicide emitters based on c-Si, poly-Si and a-Si, these gate voltages are 76 V, 63 V, and 69 V, respectively. Compared with c-Si, poly Si and a-Si field emitters, the application of Mo silicide on the same silicon field emitters exhibited 9.6 times, 2.1 times, and 4.2 times higher maximum emission current, and 6.1 times, 3.7 times, and 3.1 times lower current fluctuation, respectively. Moreover, the emission currents of the silicide FEAs depending on vacuum level are almost same in the range of 10^-9~10^-6 torr. This result shows that silicide is robust in terms of anode current degradation due to the absorption of air molecules     

Energy pay-back time and life-cycle CO2 emission of residential PV power system with silicon PV module

The concerns about environmental impacts of photovoltaic (PV) power systems are growing with the increasing expectation of PV technologies. In this paper, three kinds of silicon-based PV modules, namely single-crystalline silicon (c-Si), polycrystalline silicon (poly-Si) and amorphous silicon (a-Si) PV modules, are evaluated from the viewpoint of their life-cycle. For the c-Si PV module it was assumed that off-grade silicon from semiconductor industries is used with existing production technologies. On the other hand, new technologies and the growth of production scale were presumed with respect to the poly-Si and a-Si PV modules. Our results show that c-Si PV modules have a shorter energy pay-back time than their expected lifetime and lower CO₂ emission than the average CO₂ emission calculated from the recent energy mix in Japan, even with present technologies. Furthermore the poly-Si and the a-Si PV modules with the near-future technologies give much reduction in energy pay-back times and CO₂ emissions compared with the present c-Si PV modules. The reduction of glass use and the frameless design of the PV module may be effective means to decrease them more, although the lifetime of the PV module must be taken into account. © 1998 John Wiley & Sons, Ltd.     

A formation of cobalt silicide on silicon field emitter arrays byelectrical stress

A novel process utilizing electrical stress is proposed for the formation of Co silicide on single crystal silicon (c-Si) FEAs to improve the field emission characteristics. Co silicide FEAs formed by electrical stress (ES) exhibited a significant improvement in turn-on voltage and emission current compared with c-Si FEAs. The improvement mainly comes from the lower effective work function of Co silicide and less blunting of tips during silicidation by electrical stress in an ultra high vacuum (UHV) environment less than 10^-8 torr     

非晶硅薄膜的基本性质及其在台面型硅器件上的钝化作用

利用非晶硅薄膜的半绝缘特性将它作为硅器件,尤其是台面型硅器件的钝化保护膜,经过长达两年的实验和生产上的试用,证实了它具有特殊的优点.α-Si:H薄膜中的氢能直接填补c-Si界面上的缺陷态,降低界面态密度,使器件反向漏电流大大下降,从而改善了硅器件的稳定性,提高了可靠性与成品率,具有明显的经济效益     

Bottom-gate poly-Si thin film transistors using XeCl excimer laserannealing and ion doping techniques

High mobility bottom-gate poly-Si thin film transistors (TFTs) have been successfully fabricated on a hard glass substrate using XeCl excimer laser annealing and ion doping techniques. The authors used an a-Si:H film which is deposited by a plasma-enhanced chemical vapor deposition (PECVD) as a precursor film, and then they crystallized the a-Si film by XeCl excimer laser annealing. The maximum field effect mobility and grain size obtained were 200 cm²/V-s (n-channel), and 250 nm, respectively. The poly-Si TFTs showed excellent transfer characteristics, and an ON/OFF current ratio of over 10⁶ was obtained. Successful control of the threshold voltage within 4 V using an ion doping technique is also demonstrated     

Silicide application on gated single-crystal, polycrystalline andamorphous silicon FEAs. II. Co silicide

For pt. I see ibid., vol.48, no.1, p.149-54 (Jan. 2001). For enhancement and stabilization of electron emission, Co silicides were formed from Co, Co/Ti and Ti/Co layers on silicon FEAs. Since Ti prevents oxygen adsorption on the Co film during silicidation, uniform and smooth Co silicide layers can be obtained by depositing Co first and then Ti on silicon tips, followed by rapid annealing. Among Co silicide FEAs, Co silicide formed from Ti/Co bi-layers shows the lowest leakage current, the highest failure voltage over 152 V and the largest anode current over 1 mA at the gate voltage of 150 V. Compared with silicon field emitters, the silicide FEAs formed from Ti/Co layers exhibited a significant improvement in maximum emission current, emission current fluctuation and stability, and failure voltage     

Effect of diamond-like carbon coating on the emissioncharacteristics of molybdenum field emitter arrays

We have studied the electron emission characteristics of Mo field emitter arrays (FEAs) using a diamond-like carbon (DLC) film deposited by a layer-by-layer technique using plasma enhanced chemical vapor deposition. The turn-on voltage was lowered from 55 to 30 V by a 20 nm thick hydrogen-free DLC coating and maximum emission current was increased from 166 to 831 μA. Also the gate voltage required to get the anode current of 0.1 (μA/emitter) decreases from 77 to 48 V. Furthermore, the emission current from DLC coated Mo FEAs is more stable than that of noncoated Mo FEAs     

Integration and characterization of amorphous silicon thin-filmtransistor and Mo-tips for active-matrix cathodes

We have designed and monolithically integrated amorphous silicon thin-film transistor (a-Si TFT) with Mo-tip field emitter arrays (FEAs) on glass substrate for active-matrix cathodes (AMCs) in field-emission display (FED) application. In our AMCs, a light shield layer of metal was introduced to reduce the photo leakage and back channel currents of a-Si TFT. The light shield was designed to have the role of focusing grid to focus emitted electron beams from the AMC on the corresponding anode pixel by forming it around the Mo-tip FEAs as well as above the a-Si TFT. The thin film depositions in a-Si TFTs were performed at a high temperature of above 360°C to guarantee the postvacuum packaging process of cathode and anode plates in FED. Also, a novel wet etching process was developed for n⁺-doped-a-Si etching with high etch selectivity to intrinsic a-Si and good etch controllability and was used in the fabrication of inverted stagger TFT with a very thin active layer. The developed a-Si TFTs had good enough performance to be used as control devices for AMCs with Mo-tip emitters. The fabricated AMCs exhibited very effective aging process for field emitters     

Passivation of p-n junction in crystalline silicon by amorphous silicon

Hydrogenated amorphous silicon, a-Si:H, is shown to be an excellent passivant for crystalline silicon (c-Si) p-n junctions. A two-orders-of-magnitude reduction in reverse leakage current from that of a typical thermal oxide passivated junction is obtained. This is achieved through a lowering of the interface state density by hydrogenation of the c-Si surface. Superior bias-temperature stability of the passivated junctions also is observed. There is evidence that the hydrogen in the bulk of the a-Si:H can act as a hydrogen reservoir for rehydrogenation of the interface between c-Si and a-Si:H. Thermal stability of the a-Si:H is adequate for temperatures up to 500°C for 30 min, which is sufficient for most device-processing requirements. Above 550°C, significant dehydrogenation from both the interface and the bulk a-Si:H regions and an increase in leakage are observed. The passivation properties were assessed through studies of the current-voltage and current-temperature characteristics of the p-n junctions.     

Crystallization of μc-Si on plastic substrate by using a pulsed double-frequency YAG laser

Thin film transistors （TFTs） of microcrystalline silicon （μc-Si） can provide higher mobility and stability than that of a-Si and better uniformity than that of poly-Si TFTs, and it would be more suitable to be applied to larger-area AMOLEDs. By using 2coYAG laser ann. ealing, crystalline μc-Si thin film on plastic substrate has been investigated and the proper laser energy needed for crystallization has been indicated. It has been found that the dehydrogenation process at 300-450℃ for a few of hours could be omitted by decreasing the H content in the crystallization precursor, which is suitable for laser crystallization on plastic substrates. The crystalline volume fraction （Xc） and the grain size of the resulted μc-Si could be adjusted by controlling the laser energy. By this method, the μc-Si on plastic substrate with Xc and grain size is respectively 85% （at the maximum） and 50 nm.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Characterization of stress in doped and undoped polycrystalline silicon before and after annealing or oxidation with laser raman spectroscopy

Stress in polycrystalline silicon (poly-Si) was characterized with laser Raman spectroscopy. Effects of diffusion of phosphorus, annealing and oxidation on stress were especially studied. Relaxation of undirectional stress by annealing and oxidation was observed. Undirectional stress was relaxed by heavy doping of phosphorus which made a grain size larger. Compressive stress increased, however, by oxidation in poly-Si with a smaller grain size.     

Electric field-enhanced metal-induced lateral crystallization and P-channel poly-Si TFTs fabricated by it

The poly-Si thin film was obtained by electric field-enhanced metal-induced lateral crystallization technique at low temperature. Raman spectra, X-ray diffraction (XRD) and scan electron microscope (SEM) were used to analyze the crystallization state, crystal structure and surface morphology of the poly-Si thin film. Results show that the poly-Si has good crystallinity, and the electric field has the effect of enhancing the crystallization when DC electric voltage is added to the film during annealing. Secondary ion mass spectroscopy (SIMS) shows that the metal Ni improves the crystallization by diffusing into the a-Si thin film, so the crystallization of the lateral diffused region of Ni is the best. The p-channel poly-Si thin film transistors (TFTs) were fabricated by this large-size grain technique. The I_DS−V_DS and the transfer characteristics of the TFTs were measured, from which, the hole mobility of TFTs was 65 cm²/V s, the on and off current ratio was 5×10⁶. It is a promising method to fabricate high-performance poly-Si TFTs at low temperature for applications in AMLCD and AMOLED.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation

Excellent n-channel poly-Si thin-film transistors (poly-Si TFTs) have been formed by using retrograde channel scheme with channel doping implantation and extra counter-doping implantation. As compared to the conventional sample with undoped channel layer, a much smaller leakage current can be achieved by boron-doping the poly-Si channel layer, due to a significantly reduced depletion region. However, the on-state characteristics are degraded. A retrograde channel scheme, implemented by further phosphorus counter-doping the surface of the boron-doped channel layer, is proposed for lowering the channel surface doping concentration without changing the bulk channel doping concentration. By using the retrograde channel scheme, an off-state leakage current as low as that for the normal channel-doping scheme may be achieved, while yielding excellent on-state I-V transfer characteristics.     

The characteristics of tunnel oxides grown on textured siliconsurface with a simple and reliable process

In this work, a simple and reliable method to fabricate a textured Si surface and the characteristics of oxides grown on the textured Si surface are proposed. The concept of different oxidation rates in poly-Si grain and grain boundaries has been used to form textured Si surface which does not need to etch the surface of Si wafer and is without the constraint of stopping the oxidation process on the poly Si/Si-substrate interface to get better electrical characteristics. Tunnel oxide grown on the textured single crystalline Si exhibits much better electrical characteristics and reliabilities than those of oxides grown on poly-Si substrate (thin poly-Si film on Si substrate) and on untextured single crystalline Si substrate     

Optimization of n/i and i/p buffer layers in n-i-p hydrogenated microcrystalline silicon solar cells

Hydrogenated microcrystalline silicon (μc-Si:H) intrinsic films and solar cells with n-i-p configuration were prepared by plasma enhanced chemical vapor deposition (PECVD). The influence of n/i and i/p buffer layerson the μc-Si:H cell performance was studied in detail. The experimental results demonstrated that the efficiency is much improved when there is a higher crystallinity at n/i interface and an optimized a-Si:H buffer layer at i/p interface. By combining the above methods, the performance ofμc-Si:H single-junction and a-Si:H/μc-Si:H tandemsolar ceils has been significantly improved.     

Polished TFT's: surface roughness reduction and its correlation todevice performance improvement

Chemical-mechanical polishing (CMP) has been applied to the fabrication of n-channel polysilicon thin film transistors (poly-Si TFT's). Three different polishing conditions are compared: (1) polishing before; (2) polishing after; and (3) both polishing before and after the a-Si recrystallization. Devices with no polishing act as control samples. Experiments consistently reveal that devices with post-anneal polishing exhibit the best performance, Two-fold improvement of drain current is attributed to the smoother active polysilicon surface. The electrical characteristics of a post-anneal polished TFT in terms of field effect mobility μ_FE, threshold voltage V_T, and subthreshold swing S can be further improved if hydrogenation is employed. It is also found that a large decrease in the poly-Si surface roughness leads to higher dielectric breakdown strength and improved short-channel effects. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) results are presented and correlated with electrical results     

Performance of bifacial HIT solar cells on n-type silicon substrates

The performance of amorphous silicon(a-Si:H) /crystalline silicon(c-Si) heterojunction is studied,and the effects of the emitter layer thickness,doping concentration,intrinsic layer thickness,back heavily-doped n layer,interface state and band offset on the optical and electrical performance of bifacial heterojunction with intrinsic thin-layer(HIT) solar cells on ntype silicon substrates are discussed.It is found that the HIT solar cells on n-type substrates can obtain a higher conversion efficiency than th...     

Silicon nitride thin-film deposition by LPCVD with in situ HF vaporcleaning and its application to stacked DRAM capacitor fabrication

Silicon nitride film deposited by LPCVD with newly developed in situ HF vapor cleaning has been studied and applied to fabricate dielectric films for stacked DRAM capacitors. Using this method, an oxide-free surface of underlaid poly-Si can be obtained. Silicon nitride film deposited on this surface has been verified by FTIR measurement to have the stoichiometrically proper composition of Si₃N₄ . However, the film was found to be selectively deposited on poly-Si electrodes. This selective deposition degrades the reliability of the stacked capacitor, because the silicon nitride can not completely cover the periphery of poly-Si electrodes on SiO₂. We propose a simple process that avoids the problem making it possible to apply silicon nitride film to stacked-capacitor fabrication. Stacked capacitors fabricated by this process exhibit very low leakage current and high electrical reliability even for ultra-thin silicon nitride films less than 5 nm thick