SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.     

Low-power interface circuits between adiabatic and standard CMOS circuits

The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 μm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.     

CMOS RF integrated circuits at 5 GHz and beyond

A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RFIC) technology in unprecedented ways. These pressures are stimulating novel solutions that allow RFICs to enjoy more of the benefits of Moore's law than has been the case in the past. In addition to regular raw transistor speed increases, the growing number of interconnect layers allows the realization of improved inductors, capacitors, and transmission lines. A deeper understanding of noise at both the device and circuit level has improved the performance of low noise amplifiers (LNAs) and oscillators. Finally, an appropriate raiding of circuit ideas dating back to the vacuum tube era enables excellent performance, even when working close to the limits of a technology. This paper surveys some of these developments in the context of low-power RF CMOS technology, with a focus on an illustrative implementation of a low-power 5-GHz wireless LAN receiver in 0.25-μm CMOS. Thanks to these recent advances in passive components and active circuits, the blocks comprising the receiver consume a total of approximately 37 mW. These blocks include an image-reject LNA, image-reject downconverter, and a complete frequency synthesizer. The overall noise figure is 5 dB, and the input-referred third-order intercept (IIP3) is -2 dBm. To underscore that 5 GHz does not represent an upper bound by any means, this paper concludes with a look at active circuits that function beyond 15-20 GHz, and a characterization of on-chip transmission lines up to 50 GHz, all in the context of how scaling is expected to shape future developments     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

GaAs optoelectronic mixer operation at 4.5 GHz

Optoelectronic heterodyne detection of high-frequency intensity modulation signals using a GaAs photoconductive mixer is reported. Flat response for optical modulation frequencies up to 4.5 GHz is observed for downconversion to a 500-MHz intermediate frequency using a low power local oscillator. Heterodyne responsivity was enhanced significantly over direct detection with the same photoconductive detector due to improved contact performance under RF bias.     

26-34 GHz CMOS mixer

A 26-34 GHz fully integrated CMOS down mixer is presented. At 30 GHz RF frequency and 2.5 GHz IF frequency, 50 /spl Omega/ terminations, 5 dBm LO and 1.2 V/spl times/17 mA supply power, the circuit yields a conversion loss of 2.6 dB, an SSB NF of 13.5 dB and an IIP3 of 0.5 dBm.     

SOI and bulk CMOS frequency dividers operating above 15 GHz

Dual-phase dynamic pseudo-NMOS ([DP]²) frequency dividers have been implemented in a partially scaled 0.1 μm CMOS technology. For 4:1 dividers on silicon-on-insulator (SOI) and bulk substrates, the maximum speed, power consumption, and extracted [DP]² latch delays are 18.75 and 15.4 GHz, 13.5 and 9.8 mW and 13.3 and 16.2 ps, respectively, at 1.5 V     

CMOS and SiGe bipolar circuits for applications up to 110 GHz

Recently, CMOS has been demonstrated to be a viable technology for very-high-bit-rate broad-band and wireless communication systems up to 40 Gb/s and 50 GHz. Advances in device scaling and doping-profile optimization have also resulted in SiGe bipolar transistors with impressive performance, including cut-off frequencies of more than 200 GHz. This paper presents advances in circuit design which fully exploit the high-speed potential of a 0.13 µm CMOS technology up to 50 GHz and of a high-performance SiGe bipolar technology up to 110 GHz operating frequency. The combination of advanced circuit techniques and a state-of-the-art fabrication-process technology results in continuing the upward shift of the frequency limits.     

A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digitalconverter using fully-differential current-mode circuit techniques

Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-μm n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 db (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm²/b, respectively     

Schottky junction transistor-micropower circuits at GHz frequencies

Numerical simulations of a new micropower transistor configuration are presented. The transistor is a majority carrier device that operates as a current-controlled current-source. Results from a 0.5 μm gate length device indicate a cutoff frequency in the GHz range, for drain currents appropriate to micropower circuit applications     

Design of a high-gain FET amplifier operating at 4.4-5.0 GHz

Described here is the design and the electrical performance of a MESFET amplifier featuring an output power of 1 W with a gain of 34 dB over the frequency range from 4.4 to 5.0 GHz. The key elements that allowed the achievement of this performance were: high-gain power MESFET's, a circuit design technique based on power characterization of the MESFET's, and a low-parasitics integrated microstrip construction. The amplifier is intended to replace a medium power TWT in a telecommunication system. When compared with a typical 1-W TWT this solid-state amplifier not only requires a much simpler power supply, is lighter and has perhaps higher reliability, but also has some better electrical performances; this should result in better system performance.     

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [forGPS receiver]

In recent years, much research has been carried out on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies, for radio-frequency (RF) applications. An example of such an application is the Global Positioning System (GPS). One of the important bottlenecks to make the transition to pure CMOS is the immunity of the circuits against electrostatic discharge (ESD). This paper shows that it is possible to design a low-noise amplifier (LNA) with very good RF performance and sufficient ESD immunity by carefully co-designing both the LNA and ESD protection. This is demonstrated with a 0.8-dB noise figure LNA with an ESD protection of -1.4-0.6 kV human body model (HBM) with a power consumption of 9 mW. The circuit was designed as a standalone LNA for a 1.2276-GHz GPS receiver. It is implemented in a standard 0.25-μm 4M1P CMOS process     

2.1GHz CMOS低噪声放大器

采用上海华虹NEC0.35μm标准CMOS工艺进行RFCMOS窄带低噪声放大器的设计和制作。测试结果表明,在2.1GHz时,输入驻波比1.1,输出驻波比1.5,增益18dB,噪声系数2.7dB,P-1dB输出功率9dBm。     

High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz

The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-/spl mu/m CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.     

A low-power CMOS super-regenerative receiver at 1 GHz

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-μm CMOS process is described. The receiver includes a low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuit with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm ². The power consumption is less than 1.2 mW at V_DD=1.5 V. A 100-kHz sawtooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency     

Broadband cryogenic parametric amplifier operating at 11.6 GHz

A machine-cooled cryogenic parametric amplifier that operates at 20 K is described. The 2-stage amplifier has a 0.5 dB bandwidth of 600 MHz at 20 dB gain and an effective input noise temperature in the range 47?51 K over the frequency band of 11.3 to 11.9 GHz     

Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz

In this paper, a complementary metal oxide semiconductor (CMOS) frequency doubler for wireless applications at Ka-band is presented. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90 nm silicon on insulator (SOI) technology. All impedance matching, filter and bias elements are implemented on the chip, which has a very compact size of 0.37 mm/spl times/0.27 mm. At an output frequency of 27 GHz, source/load impedances of 50 /spl Omega/, a supply voltage of 1.25 V, a supply current of 8 mA and an input power of -4.5 dBm, a conversion gain of 1.5 dB was measured. To the knowledge of the authors, the circuit has by far the highest operation frequency for a CMOS frequency multiplier reported to date and requires lower supply power than circuits using leading edge III/V and silicon germanium (SiGe) technologies.     

Ultra-broadband 20.5-31 GHz monolithically-integrated CMOS power amplifier

A fully monolithically-integrated power amplifier with a bandwidth (-3 dB) from 20.5 to 31 GHz was realised in a 0.13 /spl mu/m standard CMOS technology. A maximum power added efficiency of 13% with a corresponding output power of 13 dBm was achieved at 25.7 GHz with 1.5 V supply voltage.     

A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5–6 GHz CMOS LNA

The increasing mask costs of modern scaled CMOS makes silicon area precious. Meanwhile, the lowering oxide thickness seriously toughens ESD protection of RF circuits, pushing towards area-demanding inductor-based ESD protection techniques. This paper presents a transformer-based ESD protection technique for inductor-based LNAs. With no area penalty, an ESD protection level of 4.5 kV HBM is achieved. Introducing two-stage protection increases the robustness up to 7.3 kV, maintaining excellent RF performance. Further it extends the TLP protection level from 3.2 to 5 A. A noise figure of 2.6 dB is achieved with a power gain of 14.8 dB, while consuming 6.5 mW. The technique serves as a solution for low-area highly protected LNAs in deep-submicron CMOS.