一种新颖的OTA结构的数模转换器

介绍了一种新颖结构的数模转换器，此转换器的设计核心是采用跨导运算技术，由CMOS运算跨导放大器（OTA）构成。此D／A转换器以模拟电流作为主要信号变量，以跨导运算放大器取代电压运算放大器，以基于OTA的有源元件取代部分无源元件，通过改变OTA的偏置电流，从而改变其互导增益gm和电压放大器增益Au，更适合于IC的集成。采用9个OTA构成一个8位的加法电路，8个OTA的互导增益gm对应8位的数字信号，8个MOS管作为开关运用由8位的数字信号控制，从而实现数字信号到模拟信号的转换。     

A Compact Four-Wavelength Quantum-Cascade Laser Source

A four-wavelength quantum-cascade (QC) laser source that operates using a single current channel is presented. The source includes two different heterogeneous cascade QC lasers, one with emission wavelengths of 7.0 $mu{hbox {m}}$ and 11.2 $mu{hbox {m}}$, and the other with 8.7 $mu{hbox {m}}$ and 12.0 $mu{hbox {m}}$ . For 3.0-mm and 3.5-mm cavity lengths, QC lasers with emission wavelengths of 8.7, 11.2, and 12.0 $mu{hbox {m}}$ have threshold current densities within less than a factor of 2, which allows them to be conveniently driven in series by a single current source.      

Enhancement-Mode$hboxSi_3hboxN_4hbox/AlGaN/GaN$MISHFETs

Enhancement-mode$hboxSi_3hboxN_4/hboxAlGaN/GaN$metal–insulator–semiconductor HFETs (MISHFETs) with a 1-$muhboxm$gate footprint are demonstrated by combining$hboxCF_4$plasma treatment technique and a two-step$hboxSi_3hboxN_4$deposition process. The threshold voltage has been shifted from$-$4 [for depletion-mode HFET] to 2 V using the techniques. A 15-nm$hboxSi_3hboxN_4$layer is inserted under the metal gate to provide additional isolation between the gate Schottky contact and AlGaN surface, which can lead to reduced gate leakage current and higher gate turn-on voltage. The two-step$hboxSi_3hboxN_4$deposition process is developed to reduce the gate coupling capacitances in the source and drain access region, while assuring the plasma-treated gate region being fully covered by the gate electrode. The forward turn-on gate bias of the MISHFETs is as large as 7 V, at which a maximum current density of 420 mA/mm is obtained. The small-signal RF measurements show that the current gain cutoff frequency$(f_T)$and power gain cutoff frequency$(f_max)$are 13.3 and 23.3 GHz, respectively.     

CMOS Active Inductor Linearity Improvement Using Feed-Forward Current Source Technique

MOSFET drain current second-order nonlinearity has a significant impact on the linearity of current regulated CMOS active inductors. It tends to compress MOSFET transconductance $(g_{m})$ by generating excess dc current $(I_{rm EX})$ in the channel, which is a function of incoming input signal amplitude. This generated excess dc current can change the original dc operating point of the current regulated CMOS active inductor, and thus, influence the inductance. Unfortunately, MOSFET drain current second-order nonlinearity contributes more to MOSFET $g_{m}$ compression than MOSFET drain current third-order nonlinearity. In this paper, a new technique known as feed-forward current source (FFCS) has been proposed to improve the linearity of the active inductor. The proposed FFCS technique makes use of the second-order nonlinear property of a MOSFET that generates $I_{rm EX}$ when an input ac signal is applied. The generated $I_{rm EX}$ is then fed-forward to the current source of the active inductor to drain out the $I_{rm EX}$ in the active inductor. This prevents the dc operating point from shifting and improves its inductance linearity. Single-ended and differential active inductors with the proposed FFCS circuit have been fabricated using Silterra's CMOS 0.18-$mu{hbox{m}}$ technology to verify the proposed technique.      

Feedforward-Regulated Cascode OTA for Gigahertz Applications

A very high-frequency operational transconductance amplifier (OTA) with a new feedforward-regulated cascode topology is demonstrated in this paper. Experimental results show a bandwidth of 10 GHz and a large transconductance of 11 mS. A theoretical analysis of the OTA is provided which is in very good agreement with the measured results. We also carry out a Monte Carlo simulation to determine the effect of transistor mismatches and process variations on the transconductance and input/output parasitic capacitances of the OTA. The linearity and intermodulation distortion properties of the OTA, which are of particular interest in microwave applications, are experimentally determined using a purpose-built single-stage amplifier. For high-frequency demonstration purposes we built a larger circuit: an inductorless microwave oscillator. The fabricated oscillator operates at 2.89 GHz and has a significantly larger output voltage swing and better power efficiency than other inductorless oscillators reported in the literature in this frequency range. It also has a very good phase noise for this type of oscillators: ${-}116$ dBc/Hz at 1-MHz offset.      

A Simplified Design Model for Random Process Variability

A method for modeling the effects of random process variation through measured transistor current is introduced. The methodology culminates by modeling random current variation at a given operating point above threshold as a zero-mean Additive White Gaussian Noise (AWGN) current source with a standard deviation dependent on nominal operating current and design variables, the transistor sizes, W and L, and the transistor operating points, $V_{gs}$ and $V_{ds}$. The model has a simple posynomial form and is accurate compared to measured data within an RMS error of 5.4% for narrow-, wide-, short-, and long-channel transistors. The model's simplified form bridges the gap between existing statistical methods and circuit design. The efficacy of the model in the circuit design space will also be presented. In the analog domain, we will show that the contributions of this model can be used as a replacement for Monte Carlo methods for calculating circuit voltage and current variances. In the digital space, we will investigate the calculation of timing delay distributions. Results calculated via an alpha-power $(alpha_{p})$ law model for average current show that scaling the supply voltage by $gamma$ results in an approximately $1/gamma^{alpha_{p}+1.1}$ scaling in the path-delay standard deviation for a 65-nm process.      

基于跨导放大器的电流模式积分单元的设计

在集成电路系统中,各种模拟功能的电流单元都是由基本的电流模单元组成。跨导放大器是电流模电路的基本单元。基于跨导放大器的电流模积分器可以实现电流到电流的积分转换。同时可应用于各种集成滤波电路的设计。在此采用0．18ptmCMOS仿真工艺,使用共源共栅结构设计一款供电电压为1．8V的高增益低功耗的跨导放大器,采用具有PTAT基准电流源的偏置电路,使用HSpice进行优化设计,并将此放大器应用于电流模式积分单元的电路仿真。     

Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET low-frequency noise occurring under switched gate bias conditions and forward substrate bias. The effect of forward substrate bias on noise reduction is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency ${rm gm}/{rm Id}$ and intrinsic voltage gain ${rm gm}/{rm gds}$ showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.      

Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters

Recent progress of wide-band communication systems demands high-frequency circuits. Conventionally, the linearity of the operational transconductance amplifier and capacitor (OTA-C) has been analyzed using Taylor series expansion. Unfortunately, this approach does not predict the frequency-dependent linearity degradation. Thus, to properly design linearized OTAs, the frequency dependence of these coefficients must be determined. In this paper, we present a frequency-dependent harmonic-distortion analytical method applied to a linear-enhanced OTA. This OTA, which is suitable for high-frequency operation, uses three linearization techniques simultaneously: 1) attenuation through floating-gate MOS transistors; 2) source degeneration; and 3) polynomial cancellation techniques. By using the harmonic-distortion analysis, some properties on the performance of OTA are used to improve the performance of OTA-C based circuits at high frequencies. A 0.5-/spl mu/m CMOS OTA simulation and experimental results are shown to verify the harmonic-distortion analytical method.     

14-GHz GaNAsSb Unitraveling-Carrier 1.3-$muhbox{m}$ Photodetectors Grown by RF Plasma-Assisted Nitrogen Molecular Beam Epitaxy

We report on picosecond pulsed response and 3-dB cutoff frequency of 1.3-$ muhbox{m}$ GaNAsSb unitraveling-carrier photodetectors (PDs) grown by molecular beam epitaxy using a radio-frequency plasma-assisted nitrogen source. The 0.1-$muhbox{m}$ -thick GaNAsSb photoabsorption layer contains 3.5% of N and 9% of Sb, resulting in a bandgap of 0.88 eV. The dark current densities at 0 and $-$9 V are 6 and 34 $hbox{mA}/hbox{cm}^{2}$, respectively. The GaNAsSb UTC PDs exhibit a temporal response width of 46 ps and a record 3-dB cutoff frequency of 14 GHz at $-$9 V.      

A Low-Supply-Voltage CMOS Sub-Bandgap Reference

A low-power (21 $muhbox{W}$ ) bandgap reference source that is operable from a nominal supply voltage of 1.4 V is described. The circuit provides an output voltage equal to the bandgap voltage having a low output resistance and allows resistive loading. It does not use resistors or operational amplifiers. Thus, the design is suitable for fabrication in any digital CMOS technology. The circuit uses a current conveyor and current mirrors to convert the proportional to absolute temperature voltage into a current using a MOSFET. The current is converted back to a voltage by using the functional inverse of the FET $v-i$ characteristics. This makes the voltage gain linear and temperature independent. The absence of back-gate bias is the reason for achieving the low supply voltage of operation. Simulation results using the transistor models for the 0.18-$mu$m TSMC process show that the voltage-variation over the temperature range 0 to 100 $^{circ} {hbox {C}}$ is $≪$1 mV.      

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25 $^{circ}hbox{C}$) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200 $^{circ}hbox{C}$. The diodes show stable operation under continuous forward current injection at 20 $hbox{A/cm}^{2}$ and under continuous reverse bias of 8 kV at 125 $^{circ}hbox{C}$. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 $hbox{A}/muhbox{s}$, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25 $^{circ}hbox{C}$–175 $^{circ}hbox{C}$.      

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation

A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 $mu{hbox {m}}$ CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 $muhbox{F}$ , and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 $mu{hbox {s}}$ for a load change of 160 mA to 10 mA, and 25 $mu{hbox {s}}$ for a load change of 10 mA to 160 mA.      

Effect of Gate Dopant Diffusion on Leakage Current in n+Poly-Si/HfO2 and Examination of Leakage Paths by Conducting Atomic Force Microscopy

The effect of gate dopant diffusion on leakage current has been investigated in $hbox{n}^{+}hbox{poly-Si}/hbox{HfO}_{2}$ capacitors. The $hbox{HfO}_{2}$ films with low gate doping concentration exhibited very low leakage currents, whereas the films with heavy gate doping concentration showed excessive leakage currents. Conducting atomic force microscopy was applied to examine the current images of the $hbox{HfO}_{2}$ films showing excessive leakage currents, and evident leakage paths with annular shape were observed. The leakage paths observed in the $hbox{HfO}_{2}$ films with heavy doping poly-Si gate may be related to the diffusion of the excessive dopant from the $hbox{n}^{+}$ poly-Si gate into the $hbox{HfO}_{2}$ , particularly through the grain boundaries in the films. This may significantly increase the leakage currents in the $hbox{n}^{+}hbox{poly-Si}/hbox{HfO}_{2}$ devices.      

A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA

This paper proposes a circuit to linearize the signal current and improve the distortion characteristics at the input of a current-mode circuit. Input voltage-to-current (V/I) conversion is carried out by a resistor that connects the signal source and the current input terminal of the current-mode circuit. The signal current flowing into the current-mode circuit through this resistor is distorted because of the signal-dependent voltage change at the current input terminal, and it is linearized by injecting a current that is proportional to the signal-dependent voltage change at the current input terminal, into the same current input terminal of the current-mode circuit. A current-mode sample-and-hold amplifier (SHA) that adopts the proposed scheme was fabricated and a 0.35-$mu{hbox {m}}$ CMOS process was used to verify the effectiveness of the scheme. It operated from a 2-V supply voltage in the analog part and a 2.5 V in the digital part with a 100-MHz clock and realized a 77- and a 86-dB spurious-free dynamic range values for 0 and $-$10 dB of full-scale signal current level $(pm hbox{100} mu{hbox {A}})$, respectively, of the 1-MHz signal input. More than a 13-bit equivalent SFDR for $-$14 to $-$4 dB of full-scale input was obtained, proving the effectiveness of the proposed scheme at realizing distortionless signal current processing.      

94 GHz Folded Fresnel Reflector Using C-Patch Elements

A 94 GHz folded Fresnel reflector (FFR) for helicopter collision avoidance Radar is presented. The antenna system consists of a primary source illuminating a semi-reflecting grid that reflects the primary source polarization toward the main reflector opposite the grid. The main reflector has two functions. It focuses the field in the desired direction and rotates the incident polarization by 90$^{circ}$ to enable it to pass through the grid and radiate. Specific patch elements having a C-shape have been designed for this purpose. In order to increase overall efficiency, the reflector combines 8 correcting zones in its center and 4 at the periphery. The reflector is manufactured using standard photolithographic techniques. The primary source consists of a metal waveguide covered with a small frequency selective surface (FSS) for matching purposes. The maximum measured gain is 36.5 dBi at 94 GHz. The maximum side lobe level is ${-}18$ dB. The return loss value does not exceed ${-}25$ dB. The frequency bandwidth ${-}3$ dB in gain and return loss is 10%. In-flight measurements were conducted demonstrating the ability to detect power lines at distances up to 680 m.      

Improved synthesis of gain-boosted regulated-cascode CMOS stagesusing symbolic analysis and gm/ID methodology

A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed     

Schottky Barrier N-Type Thin Film Transistors With Polycrystalline Silicon Channel and Er-Silicided Metallic Junctions

N-type Schottky barrier thin film transistors (SB-TFTs) with polycrystalline silicon channel and metallic junctions were fabricated by using Er silicidation, and electrical structural properties were compared to conventional TFTs with phosphorous-doped source/drain regions. The performances of SB-TFTs are better than that of the conventional TFTs. A forming gas annealing process leads to a great improvement in the characteristics of both devices. In particular, excellent electrical characteristics were obtained from the forming gas annealed SB-TFTs: the subthreshold swing of 180 mV/dec, the drive current of $hbox{1.47} times hbox{10}^{-5} hbox{A}$, and the on/off current ratio of $ hbox{5} times hbox{10}^{6}$.      

A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 $mu$ m CMOS

A V-band frequency doubler monolithic microwave integrated circuit with a current re-use buffer amplifier is presented. The circuit is designed and fabricated using 0.13 $mu$m CMOS technology. The buffer amplifier uses a current re-use topology, which adopts series connection of two common source amplifiers for low dc power consumption. The suppression of the fundamental frequency is obtained by shunting the input frequency at the output node of the doubler and the drain nodes of two common-source stages of the buffer amplifier. The fabricated frequency doubler exhibits an output power of ${-}$4.45 dBm and a conversion gain of ${-}$ 0.45 dB at input frequency of 27.1 GHz with an input power of ${-}$4 dBm. The suppression of the fundamental signal is 49.2 dB. The total dc power dissipation is 9 mW while the buffer amplifier consumes 5 mW. The integrated circuit size including pads is 1.24 mm$, times ,$0.75 mm. To our knowledge, this is the highest suppression with low-power dissipation among V-band frequency doublers.      

Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height $(Phi_{B}^{N})$ of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in $Phi_{B}^{N}$ is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.