一种GSM无线发射系统中的低功耗数模转换器

针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源...     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

An 8-bit, 5 ns monolithic D/A converter subsystem

Describes a 5 ns settling time digital-to-analog converter device, which has been designed for use in video speed successive approximation analog to digital converters. The chip includes a precision reference source with a 25 ppm per degree C average temperature coefficient and a high-speed comparator. The successive approximation approach, restricted to low-speed converters until now, has the advantages of low cost and straightforward drive requirements. The achievement of the operating speeds described is dependent both on the circuit techniques used and the process employed. The DAC circuit, unlike most other devices, uses a multiple-matched current source array technique, which leads to a very linear, low glitch output. Without any form of trimming, most functional devices meet a /spl plusmn//SUP 1///SUB 2/ LSB differential and integral linearity specification, and many are /spl plusmn//SUP 1///SUB 4/ LSB or better.     

Nyquist电流型7位20MHz采样率CMOS数模转换器

介绍了一种高速7位DAC的设计及芯片测试结果,该DAC选取高5位单位电流源,低2位二进制电流源的分段结构。考虑了电流源匹配、毛刺降低以及版图中误差补偿等方面的问题来优化电路。流片采用0.35μmChartered双层多晶四层金属工艺,测试结果表明在20 MH z的采样频率下,微分非线性度和积分非线性度分别小于±0.2 LSB和±0.35 LSB。该DAC的满幅建立时间是20 ns,芯片面积为0.17 mm×0.23 mm。电源电压为3.3 V,功耗为3 mW。     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.     

一种电流自校准14位、50Msample/s CMOS DAC

文章介绍一种14位、50Msample/s的电流驱动型CMOS DAC.该电路的核心由31个温度计编码的高5位电流源、15个温度计编码的中间4位电流源和5个二进制编码的低5位电流源构成.为了达到更高的静态线性度,一种新颖的电流自校准技术被提出,用来对最高5位的电流源进行自校准.这种自校准完全是在后台操作的,并不需要一个替代电流源去替代正在被校准的那一路电流源.该芯片采用0.25μm标准CMOS工艺制造,芯片面积为3.54mm².测试结果显示芯片的静态分辨率达到12位.     

一种用于电流舵DAC的开关顺序优化技术

提出了一种用于电流舵DAC的开关顺序优化技术。首先,将高位电流源阵列拆分成四个部分并位于四个象限中,在每个象限中采用开关顺序优化技术消除电流源阵列由PVT变化而带来的二阶梯度幅值误差;其次,对开关顺序优化后的电流源阵列根据幅值变化进行排序并重组,形成最终的电流源及开关顺序,消除了一阶梯度幅值误差和其他残余误差。与常规开关顺序优化技术相比,该技术能更有效地降低幅值误差,提高了DAC的静态性能。为了验证提出的开关顺序优化技术,基于40 nm CMOS工艺制作了一个12位200 MS/s采样频率的电流舵DAC。测试结果表明,实施开关顺序优化技术的DAC的INL、DNL分别从0.63 LSB、0.37 LSB降低到0.54 LSB、0.25 LSB。     

A 100-MHz CMOS DAC for video-graphic systems

A 6-b weighted-current-sink video digital-to-analog converter (DAC) with 10-90% rise/fall time of 4 ns, integrated with a double-metal 3-μm CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technology. Experimental results show that a conversion rate of 100 MHz is achievable. The power consumption is 150 mW and the active chip area is 0.5×1.0 mm² . The differential of 0.1 LSB demonstrates that 8 b of accuracy can be achieved. The integral linearity is 0.5 LSB     

四位GaAs超高速D/A转换电路的研究

本文简要介绍了目前国际上GaAs超高速D/A转换器的研制情况。在详细分析了几种常用类型D/A转换电路工作原理的基础上,结合现有GaAs VHSIC的制作工艺条件,设计并制作了一种4位单片集成GaAs MESFET D/A转换电路。测试结果表明,该电路分辨率为4位,转换速率办1Gs/s,建立时间小于1.0ns,微分线性误差小于±1/2LSB,功耗约为20mW。     

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 μm single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV·s and the settling time within ±0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm×1.2 mm (1.75 mm×0.7 mm for the DAC portion)     

A high-performance CMOS 70-MHz palette/DAC

A VLSI circuit has been developed that combines dual-ported RAMs and three high-speed 8-b digital-to-analog converters (DACs). It is known as a palette/DAC. A 6-2 segmented DAC architecture improves differential linearity and monotonicity. The current-source cell uses a cascode device to improve the DAC's linearity. A reference current, set by an on-chip bandgap reference voltage generator, and its associated distribution scheme eliminate the negative effects of threshold mismatches between current source cells, supply line resistance, and noise. The maximum conversion rate is 70 MHz with typical DC differential nonlinearity of 0.48 LSB (least significant bit). The 253-mil/SUP 2/ is designed on a double-metal CMOS process and consumes 1.2 W of power.     

用于触摸屏控制电路的低功耗模数转换器设计

为了降低触摸屏控制电路的功耗,本文提出了一种低功耗逐次逼近型模数转换器(SAR ADC)。对该SAR ADC所采用的电容阵列数模转换器(DAC)、比较器和逐次逼近寄存器等进行了研究与设计。首先,基于两级并串耦合电容设计电容阵列DAC结构,并设计配套的参考电平转换方案。接着,设计两级全动态比较器,并分析比较器的工作原理。然后,基于动态逻辑设计低功耗低误码逐次逼近寄存器。最后,基于180nm CMOS工艺,在1V电源电压,200kHz采样频率和96.243kHz输入频率条件下对SAR ADC进行了仿真。仿真结果表明:积分非线性误差(INL)和微分非线性误差(DNL)分别为0.222/-0.203LSB和0.231/-0.184LSB,无杂散动态范围(SFDR)为76.56dB,信噪失真比(SNDR)为61.50dB,有效位(ENOB)为9.92位,功耗为0.464μW,品质因素(FOM)值为2.4fJ/Conv.-step。本文设计的低功耗SAR ADC满足触摸屏控制电路应用要求。     

3V 10b 70 MHz CMOS D/A converter for video applications

This work describes a 10 b 70 MHz CMOS digital-to-analogue converter (DAC) for video applications. The proposed DAC is composed of a unit decoded matrix for 7 MSBs and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area and glitch energy. A new switching scheme for the unit decoded matrix is developed to further improve the linearity. Cascode current sources and differential switches with a new deglitching circuit improve the dynamic performance     

A self-trimming 14-b 100-MS/s CMOS DAC

A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm×3.44 mm in a 0.35-μm CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A 6-bit digital to analogue converter based on current mirrors

In this article, a digital to analogue converter (DAC) based on multi-weighted current sources is proposed. This research requires only three kinds of current sources for a 6-bit DAC. The proposed DAC is implemented by 0.18?µm CMOS technology. The post-layout simulations of integral nonlinearity and differential nonlinearity are 0.076 and 0.099?LSB, respectively. The core area of the chip is 640?µm². The DAC consumes 3.5?mW at the sample rate of 1.6?GHz with a supply voltage of 1.8?V. The specifications of the proposed DAC make it suitable for a portable device.     

Power efficient high-speed DAC for wideband communication applications

This paper demonstrates a power efficient design of high-speed Digital-to-Analog Converters (DACs) for wideband communication systems. For Wireless personal area network applications with a 250 MHz signal bandwidth, a 6 bit DAC capable of two times the Nyquist rate sampling is implemented in a current steering segmented 2 + 4 architecture optimized for power efficiency. Along with a proposed master-slave deglitch circuit, several circuit techniques are investigated to improve dynamic performances such as linearity. Implemented in a 0.18 um CMOS process, our DAC achieved a superior conversion performance over the state-of-the-arts, exhibiting integral nonlinearity of less than 0.27 LSB and differential nonlinearity of less than 0.15 LSB. Measured spurious free dynamic range for 251 MHz output signal is 40.92 dB, with total power consumption at 1 GS/s of 6mW, yielding a figure-of-merits of 78.3 pJ/(conversion step*W).     

基于QN旋转布局的10位500 MS/s分段电流舵DAC

针对分段电流舵数/模转换器（Digital-to-Analog Converter，DAC），通过理论分析和推导，研究电流源阵列系统失配误差和寄生效应对非线性的影响，采用电流源阵列Q^N旋转游走版图布局方案，能够减小电流源系统失配的一次误差，而且版图布线简单，由寄生效应引起的电流源失配较小，利于DAC非线性的优化.基于0.18μm CMOS，采用"6+4"的分段结构，设计了一种10位500MS/s分段电流舵DAC，流片测试结果表明，在输入频率为1.465MHz，采样速率为500MS/s的条件下，无杂散动态范围（Spurious Free Dynamic Range，SFDR）为64.9dB，有效位数（Effective Number of Bits，ENOB）为8.8 bit，微分非线性误差（Differential Non-linearity，DNL）和积分非线性误差（Integral Non-linearity，INL）分别为0.77LSB和1.12LSB.     

应用于AMOLED源极驱动的高精度DAC设计

针对OLED显示面板更高分辨率、更高精度的需求,本文提出了一种应用于高分辨率AMOLED源极驱动的高精度10bit DAC结构。设计的DAC由6bit的GAMMA校正电阻串DAC及4bit的基于尾电流源插值的输出缓冲器级联构成,达到高精度的同时占用较小的芯片面积。为进一步提高AMOLED驱动的灰阶电压精度,增加了一个DAC斜率可编程单元对线性DAC输出曲线进行进一步调节,以更好地拟合AMOLED显示屏所需的灰阶-电压曲线,此外,输出缓冲器采用尾电流源插值的方法来实现高精度的第二级DAC。在UMC 80nm CMOS工艺下,仿真结果表明设计的DAC的最大INL和DNL分别为0.47LSB、0.24LSB。在10kΩ电阻及30pF电容负载下,DAC电压从最低灰阶到最高灰阶的建立时间为3.38μs。驱动电路可以快速、精确地将图像数据转换为建立在像素电路上的电压,满足分辨率为1080×2 160驱动芯片的应用需求。     

一种带有插值滤波器的8位650MHz采样速率数字模拟转换器

针对OFDM-UWB标准超宽带收发系统中数模转换器(DAC)的要求,设计了一款8位650MHz采样速率电流驱动型数模转换器(Current-steering DAC)。为了提高静态性能,本设计通过蒙特卡洛分析确定电流源最佳尺寸并采用双中心版图技术;为了提高动态性能,文中采用共源共栅电流源结构,对开关电压降摆幅处理并在数字输入端前加入插值滤波器。测试结果表明,DAC的积分非线性(INL)和差分非线性(DNL)分别为0.3LSB和0.41LSB,650MHz转换速率下带内奈奎斯特无杂散动态范围(SFDR)为41dB。整体面积为1.8cm×1.3cm,其中DAC面积为0.8cm×0.8cm。