基于强化学习和分块并行的演化硬件方法

演化硬件（EvolvableHardware,EHW）是可编程逻辑器件和进化算法的结合,可根据不同演化目标自主动态调整自身电路结构.在演化硬件方法中,由于其自演化特性和上层遗传算法为参数敏感型,面对不同演化对象自适应性较差.同时遗传算法有早熟缺陷,在大型演化目标后期经常无法演化到目标真值表,成功率较低.本文在传统演化硬...     

三模冗余演化自修复系统设计及可靠性分析

将演化硬件与TMR技术相结合在系统级层面设计并实现了一款ETMR系统,并以马尔可夫过程理论为基础探讨了其可靠性规律.发现在任意区间上,ETMR较之单模和TMR系统具有较高可靠性,同时指出修复率与故障率比值是影响ETMR系统可靠度的主要因素,且比值越大其可靠度接近于1的区间跨度越大.系统构建方法及所得结论对于将ETMR系统应用于具体工程实践具有一定的启发和指导作用.     

外部型数字电路进化设计研究

提出了一种在恶劣环境下实现电路系统高可靠运行的新方法.简要介绍了EHW的基本概念和工作原理,以四选一多路选择器为例阐述了电路的进化设计过程,证明了演化算法的收敛性和演化硬件理论的可行性,为最终研究硬件电路的自适应和自修复奠定了基础.     

模拟型演化硬件中可重构器件的比较研究

演化硬件的研究者受困于满足可演化要求的灵活可重构硬件平台的匮乏.一方面,虽然现有商用可重构平台多数具有动态可局部重构能力,但是其设计目的不是用来研究演化硬件的.另外一方面,用户定制的面向演化硬件研究的芯片没有商用化,而且也不太可能在最近走向商用市场.本文研究了两类用来进行模拟演化硬件研究的可重构器件:商用的现场可编程模拟阵列和用户定制的现场可编程三极管阵列.通过比较研究,作者认为在FPTA类定制用于演化的可重构平台商用化之前,在FPAA平台上开展EHW的研究是有意义的,因为FPAA已经具有充分灵活的重构接口和充足的可重配置资源.     

一种新的电路设计和实现方法——进化硬件

该文介绍了一种新的电路设计和实现方法——进化硬件(EHW)。概述了进化硬件的有关概念和国内外的相关研究情况,简要介绍了有关的进化算法和进化硬件的FPGA实现方法及其应用,讨论了现阶段进化硬件在实现上存在的一些问题,并对进化硬件的发展方向和应用前景进行了展望。     

基于演化硬件的海鲜物流保鲜系统设计

针对海鲜运输中的人工保鲜的问题,利用无线的基于演化硬件（evolvablehardware,EHW）传感器技术和GPRS技术设计了一个海鲜运输途中的智能保鲜系统,该系统可以通过传感器模块实时的采集海鲜的温湿度信息,并通过GPRS网络进行数据信息的上传,在远程控制中心接收到的数据信息进行有效的信息分析处理,再控制模式库中进行模式匹配操作。然后对运输中的相应活海鲜做出有效的保鲜措施。该系统采用基于演化硬件技术改进的AM2301温湿度传感器模块作为信息采集模块,利用CC2530作为无线发射模块,整个系统实时性高,能够科学有效地解决海鲜在运输中的保鲜问题。     

两种系统级单粒子效应容错方法性能仿真分析

基于VLSI的信息处理系统空间应用时容易遭受单粒子翻转效应(SEU:Single Event Upset)的影响.基于结构冗余的三模冗余(TMR:Three Module Redundancy)和基于信息冗余的错误检纠错(EDAC:Error Detection and Correction)是两种常见的系统级抗单粒子翻转的容错方法,被广泛应用于空间信息处理系统中.从可靠性改进、存储资源占用、硬件实现代价以及实现延时等四个方面,对两种方法进行了性能分析和仿真实验.性能分析和仿真实验结果表明,EDAC方法适合应用于基本数据宽度较大、存储资源受限、实时性要求不高的应用中,结构TMR方法适合应用于基本数据宽度较小、存储资源充足、实时性要求较高的应用中.     

江苏多维展示TMR磁传感器

在美国举行的"2013传感器博览会(2013 Sensors Expo)"上,江苏多维科技有限公司(MDT)展示了其TMR(隧道磁阻)磁传感器系列,包括1微安超低功耗TMR磁开关和新开发的超低噪声TMR线性磁场传感器。MDT的TMR磁传感器专为计     

行业视点

新品推荐世界第一款TMR磁开关传感器用于电池供电流量计江苏多维科技有限公司(MDT)日前宣布推出世界上第一款TMR磁开关传感器,该种新型磁开关传感器由多维科技的TMR技术(隧道磁阻)支持,是包括接近开关、速度传感器和位置传感器的多种高性能工业类应用的最佳选择。TMR技术在磁盘驱动器行业中已经被证实是一     

演化硬件及面向演化的VLSI可重构体系结构设计

演化硬件在环境适应性和可靠性设计上具有潜在的巨大优势。文章介绍了数字和模拟电路演化综合的原理和步骤，几类典型的演化硬件平台及其局限性，重点讨论了面向演化的VLSI可重构体系结构，最后提出了这一新兴研究领域面临的一些问题及解决方法。     

Partial evaluation based triple modular redundancy for single event upset mitigation

We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault insertion simulator to evaluate partial redundancy technique on the designs from MCNC′91 benchmark. Experimental results demonstrate that we can reduce the area overhead by up to 39.18% and on average 17.23% of the hardened circuit when compared with the traditional TMR. For circuits with a large number of gates and less number of outputs, there is a significant savings in area. Smaller circuits or circuits with a large number of outputs also show improvement in area savings for increased rounding range.     

基于RHBD技术的深亚微米抗辐射SRAM电路的研究

研究了目前业内基于抗辐射加固设计(RHBD)技术的静态随机存储器(SRAM)抗辐射加固设计技术,着重探讨了电路级和系统级两种抗辐射加固方式。电路级抗辐射加固方式主要有在存储节点加电容电阻、引入耦合电容、多管存储单元三种抗辐射加固技术;系统级抗辐射加固方式分别是三态冗余(TMR)、一位纠错二位检错(SEC-DED)和二位纠错(DEC)三种纠错方式,并针对各自的优缺点进行分析。通过对相关产品参数的比较,得到采用这些抗辐射加固设计可以使静态随机存储器的软错误率达到1×10-12翻转数/位.天以上,且采用纠检错(EDAC)技术相比其他技术能更有效提高静态随机存储器的抗单粒子辐照性能。     

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs.     

一种FPGA抗辐射工艺映射方法研究

 提出一种基于部分TMR和逻辑门掩盖的FPGA抗辐射工艺映射算法FDRMap,以及一个基于蒙特卡洛仿真的并行错误注入和仿真平台.该平台和算法已经应用到复旦大学自主研发的FPGA芯片FDP4软件流程的工艺映射模块.实验结果表明,FDRMap能够在增加14.06%LUT数目的前提下,降低电路的抗辐射关键度32.62%;与单纯采用部分TMR的方法相比,在节省12.23%的LUT数目同时,还能额外降低电路关键度12.44%.     

Fault-tolerant analysis of TMR design with noise-aware logic

Due to the effect of thermal noise, ground bounce and process variations in nanometer process, the behavior of any logical circuit becomes increasingly probabilistic. In this paper, based on the noise model [5] on the input and output nodes of a probabilistic CMOS (PCMOS) gate, the correctness probabilities of four PCMOS primitive gates, NOT, NAND, NOR and XOR, can be firstly computed. Based on the concept of the probabilistic transfer matrices (PTMs) and the corresponding operations on PTMs for the serial and parallel compositions of the components in a well-formed circuit, the correctness probability of the output in a 3-input PCMOS majority circuit in a triple modular redundancy (TMR) design can be further computed. For a given circuit with smaller error, it is well known that a TMR design has good fault-tolerant characterization and the correctness probability of the original output is converged to 1. Under the use of noise-aware logic in a TMR design, it is obvious that the fault-tolerant characterization of a TMR design is degraded and the correctness probability of the original output is not converged to 1. The experimental results show that the improvement region of the correctness probability of the original output will be narrowed due to the noise effect on the gates in a 3-input PCMOS majority circuit.     

Research on the packing algorithm for anti-SEU of FPGA based on triple modular redundancy and the numbers of fan-outs of the net

Static Random Access Memory （SRAM） based Field Programmable Gate Array （FPGA） is widely applied in the field of aerospace,whose anti-SEU （Single Event Upset） capability becomes more and more important.To improve anti-FPGA SEU capability,the registers of the circuit netlist are tripled and divided into three categories in this study.By the packing algorithm,the registers of triple modular redundancy are loaded into different configurable logic block.At the same time,the packing algorithm considers the effect of large fan-out nets.The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy （TMR）.Comparing with Timing Versatile PACKing （TVPACK）,the algorithm in this study is able to obtain a 11％ reduction of the number of the nets in critical path,and a 12％ reduction of the time delay in critical path on average when TMR is not considered.Especially,some critical path delay of circuit can be improved about 33％.     

Probing tunnel barrier shape and its effects on inversed tunneling magnetoresistance at high bias

We have used an electron holography (EH) technique to directly probe the potential profile of tunnel barriers in magnetic tunnel junctions (MTJs). Barriers with under-, optimum-, or over-oxidized condition have been investigated. One important finding is that there is always slight oxidation of the top electrode because of film morphology. Sharp interfaces can be achieved in the bottom interface of optimally oxidized barrier or both interfaces in MTJs with under-oxidized barriers. We also demonstrate, theoretically and experimentally, how barrier shape affects the bias dependence and, in low barrier height case, result in inversed tunneling magnetoresistance (TMR) at high bias. The mechanism is very different from that responsible for inversed TMR in all biases. The finding leads to the possibilities of achieving better signals at high bias in real applications.     

一种基于ALU单元的改进的三模冗余结构设计

对于传统的三模冗余结构(TMR),当其中两个模块发生失效时可能出现功能相同的情况,造成三模冗余失效.为了解决这一问题,针对ALU模块的结构特点提出了对操作数编码的方法到达三个模块差异化的效果,采用此方法后能100%的消除TMR同功能失效的问题,同时此方法相对于模块的差异化设计成本更低,效果更明显.     

三模冗余在ASIC设计中的实现方法

星载计算机系统处于空间辐照环境中,可能会受到单粒子翻转的影响而出错,三模冗余就是一种对单粒子翻转有效的容错技术。通过对三模冗余加固电路特点的分析,提出了在ASIC设计中实现三模冗余的2种方法。其一是通过Syno—psys的综合工具DesignCompiler对原设计进行综合,然后修改综合后的门级网表再次综合;其二是直接建立采用三模冗余加固的库单元。     

Majority Logic Mapping for Soft Error Dependability

This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. A new type of voter circuit, that uses some knowledge from the analog design arena is proposed, together with a new mapping approach to implement circuits given their input/output table. This new mapping approach is shown to compare favorably against a classic mapping. The implementation and validation of an adder circuit, using conventional triple modular redundancy (TMR), the classic mapping, and the proposed solution are analyzed, in order to confirm that the shown technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR. Finally, implementations of a subset of the ISCAS 85 benchmark circuits using TMR with the analog voter and the proposed approach are compared and the results analyzed.