用户可重构系统芯片-U-SoC

随着深亚微米技术(DSM)的不断发展,完全专用的系统芯片(SoC)已经面临新的问题和挑战.本文在研究硅技术发展趋势、硅产品特征循环规律以及硅产业结构演变规律的基础上,提出了一种具有一定“通用“性的用户可重构系统芯片(UserreconfigurableSoC,简称U-SoC),它通过用户重构功能降低新产品的开发成本,缩短上市周期,提高设计效率,从而增强了SoC的适应性和灵活性.研究U-SoC设计方法,对于加速我国微电子产业的发展进程,实现跨越式发展有重要作用.     

用户可重构系统芯片-U-SoC

随着深亚微米技术(DSM)的不断发展,完全专用的系统芯片(SoC)已经面临新的问题和挑战.本文在研究硅技术发展趋势、硅产品特征循环规律以及硅产业结构演变规律的基础上,提出了一种具有一定"通用"性的用户可重构系统芯片(UserreconfigurableSoC,简称U-SoC),它通过用户重构功能降低新产品的开发成本,缩短上市周期,提高设计效率,从而增强了SoC的适应性和灵活性.研究U-SoC设计方法,对于加速我国微电子产业的发展进程,实现跨越式发展有重要作用.     

应用于视频处理的可重构流处理器的设计与实现

设计了一款新的应用于多媒体处理领域的可重构多媒体流处理器.该可重构多媒体流处理器采用并行处理机制,在经过算法映射后,可以充分利用多媒体算法的高并行度,同时实时处理不同的多媒体算法.该架构在Xilinx的Virtex4芯片上通过验证,并与ARM9处理器共同构成嵌入式多媒体处理平台,验证处理H.264和AVS的解码过程.     

可编程系统芯片的设计构架

本文介绍了可编程系统芯片PSoC的设计构架，包括PSoC的内核、数字模块、模拟模块的组成和构造，以及使用PSoC混合信号阵列中的模块可以构造的用户模块和功能模块。最后介绍了“动态重构”的概念。     

基于IDP卫星通信模块的远洋船舶实时监控系统

引言 本文采用ARM芯片作为控制核心．设计了一款以GPS定位模块与卫星通信模块为依托的远洋船舶实时监控系统。该系统能够按照用户要求定时上传远洋船舶的位置信息以及航向信息,解决了传统船舶定位和救援中出现的问题．保证了船舶动态监测及时、准确．可靠。同时该系统方便扩展其他功能．以便获得更广泛的应用。     

用户可重构系统芯片—U—SoC

随着深亚微米技术（DSM）的不断发展，完全专用的系统芯片（SOC）已经面临新问题和挑战。本文在研究硅技术发展趋势，硅产品特征循环规律以及硅产业结构演变规律的基础上，提出了一种具有一定“通用”性的用户可重构系统芯片（User reconfigurable Soc,简称U-SoC)，它通过用户重构功能降低新产品的开发成本，缩短上市周期，提高设计效率，从而增强了SoC的适应性和灵活性。研究U-Soc设计方法，对于加速我国微电子产业的发展进程，实现跨越式发展有重要作用。     

一种可重构数据压缩信息处理系统的设计实现

本文介绍可重构电子系统相关技术的发展现状,在分析了JPEG2000标准编解码芯片ADV212内部结构和工作原理的基础上,提出了一种可重构的数据压缩信息处理系统设计方案,它结合了FPGA器件的灵活性和专用图像数据编解码芯片的高效性,系统架构上主要运用FPGA资源实现系统重构,即运用可编程逻辑对图像数据压缩芯片ADV212进行寄存器配置、数据码流调度控制以及系统时序逻辑适配。经过图像数据的压缩解压对比测试,该数据压缩信息处理系统具有较高的峰值信噪比(PSNR),在实现了系统可重构同时,能够满足某型高速光通信系统对图像数据压缩实时性和数据完整性的要求。     

系统芯片总线分析模块的设计

提出了增加系统芯片观测性的一种新颖实现方法，即增加一个总线分析模块以实现对芯片的系统级监控。该总线分析模块由采样、存储、调试以及上位机接口单元组成。用户通过上位机软件可以方便地设置指令的采样点，选择自己需要的总线采样信号，对采样结果进行查询等。总线分析模块通过存储单元实现了对多次采样结果的存储。     

可重构技术在后SoC时代的应用——U—SoC

随着深亚微米(DSM)设计技术的发展和芯片设计复杂度的上升，完全专用的SoC系统面临新的问题和挑战，专家预测具有一定“通用”性质的系统芯片是后SoC时代的特征。本文在跟踪国际可重构技术的基础上，研究一种符合我国IC设计现状的用户可重构系统芯片，提出器件设计与应用设计分离的“片上创新应用”(Desipless)概念，并从硅技术发展规律的角度论述用户可重构系统芯片对硅产业结构下一轮分工的影响。     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

面向分组密码的可重构异构多核并行处理架构

现有的可重构分组密码实现结构中,专用指令处理器吞吐率不高,阵列结构资源利用率低、算法映射过程复杂.为此,设计了分组密码可重构异构多核并行处理架构RAMCA（Reconfigurable Asymmetrical Multi-Core Architecture）,分析了典型SP（AES-128）、Feistel（SMS4）、L-M（IDEA）及MISTY（KASUMI）结构算法在RAMCA上的映射过程.在65nm CMOS工艺下完成了逻辑综合和功能仿真.实验表明,RAMCA工作频率可达到1GHz,面积约为1.13mm²,消除工艺影响后,对各分组密码算法的运算速度均高于现有专用指令处理器以及Celator、RCPA和BCORE等阵列结构密码处理系统.     

Reliability & Safety Analysis of a Fault-Tolerant Controller

This paper analyzes a fault-tolerant, microprocessor-based controller for an electric wheelchair. Two candidate architectures are considered, including reconfigurable duplication and stand-by sparing. The difference in the reliability and safety of the two candidates is determined through the use of Markov models. Safety is paramount in the wheelchair application because of the need to protect the physically disabled wheelchair user;reliability by itself is insufficient for selecting an appropriate architecture in this application. The results show that reconfigurable duplication is safer than standby sparing even though standby sparing is more reliable. Because of the better safety, reconfigurable duplication is the preferred approach for the wheelchair application. Safety is extremely important in the selection of a fault-tolerant architecture for the electric wheelchair control system. Standby sparing provides a conceptually simple approach that achieves a higher reliability than reconfigurable duplication. However, reconfigurable duplication has a higher safety for a given fault coverage. Because of the need for safety in the electric wheelchair control system, reconfigurable duplication is the selected approach.     

面向密码算法的异步可重构结构设计

针对FPGA和ASIC在实现密码算法时的不足之处，本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供，数据通路由可重构单元之间的相互连接实现，异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后，文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中，使用改进的DSDCVS逻辑来设计其运算电路，减小了单元的面积，提高了单元的工作速度。应用实例表明，在实现密码算法时，面向密码算法的异步可重构结构表现出了比FPGA更好的性能。     

Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective

Embedded systems present significant security challenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedded systems on reconfigurable hardware and proposes a security architecture for embedded systems (SAFES). SAFES leverages the capabilities of reconfigurable hardware to provide efficient and flexible architectural support for security standards and defenses against a range of hardware attacks. The SAFES architecture is based on three main ideas: (1) reconfigurable security primitives; (2) reconfigurable hardware monitors; and (3) a hierarchy of security controllers at the primitive, system and executive level. Results are presented for reconfigurable AES and RC6 security primitives and highlight the value of such an architecture. This paper also emphasizes that reconfigurable hardware is not just a technology for hardware accelerators dedicated to security primitives as has been focused on by most studies but a real solution to provide high-security and high-performance for a system.     

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.     

A RISC architecture extended by an efficient tightly coupled reconfigurable unit

In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain reconfigurable functional unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminate the communication overhead between them. To speed up execution, the RFU exploits instruction level parallelism (ILP) and spatial computation. Also, the proposed integration of the RFU efficiently exploits the pipeline structure of the processor, leading to further performance improvements. Furthermore, a development framework for the introduced architecture is presented. The framework is fully automated, hiding all reconfigurable hardware related issues from the user. The hardware model of the architecture was synthesized in a 0.13?µm process and all information regarding area and delay were estimated and presented. A set of benchmarks is used to evaluate the architecture and the development framework. Experimental results prove performance improvements in addition to potential energy reduction.     

Application-specific coarse-grained reconfigurable array: architecture and design methodology

Coarse-grained reconfigurable arrays (CGRAs) have shown potential for application in embedded systems in recent years. Numerous reconfigurable processing elements (PEs) in CGRAs provide flexibility while maintaining high performance by exploring different levels of parallelism. However, a difference remains between the CGRA and the application-specific integrated circuit (ASIC). Some application domains, such as software-defined radios (SDRs), require flexibility with performance demand increases. More effective CGRA architectures are expected to be developed. Customisation of a CGRA according to its application can improve performance and efficiency. This study proposes an application-specific CGRA architecture template composed of generic PEs (GPEs) and special PEs (SPEs). The hardware of the SPE can be customised to accelerate specific computational patterns. An automatic design methodology that includes pattern identification and application-specific function unit generation is also presented. A mapping algorithm based on ant colony optimisation is provided. Experimental results on the SDR target domain show that compared with other ordinary and application-specific reconfigurable architectures, the CGRA generated by the proposed method performs more efficiently for given applications.     

Demonstration of an agile hybrid IP-optical packet construction mechanism in wavelength routed optical packet switched networks

This paper presents a novel architecture for an ingress edge OPS router and demonstrates a mechanism that maps Internet traffic onto optical packets. The architecture utilises a high-speed reconfigurable hardware platform and a fast tunable laser and also supports the user network interface (UNI) functionality by fully interacting with the physical and higher network layers. The main design issues, including wavelength agility, traffic aggregation based on the class of service and variable length optical packet construction and transmission are also discussed.     

A software radio architecture for linear multiuser detection

The integration of multimedia services over wireless channels calls for provision of variable quality of service (QoS) requirements. While radio resource management algorithms (such as power control and call admission control) can provide certain levels of variability in QoS, an alternate approach is to use reconfigurable radio architectures to provide diverse QoS guarantees. We outline a novel reconfigurable architecture for linear multiuser detection, thereby providing a wide range of bit error rate (BER) requirements amongst the constituent receivers of the reconfigurable architecture. Specifically, we focus on achieving this dynamic reconfiguration via a software radio implementation of linear multiuser receivers. Using a unified framework for achieving this reconfiguration, we partition functionality into two core technologies [field programmable gate arrays (FPGA) and digital signal processor (DSP) devices] based on processing speed requirements. We present experimental results on the performance and reconfigurability of the software radio architecture as well as the impact of fixed point arithmetic (due to hardware constraints)     

基于动态可重构的FFT处理器的设计与实现

提出了一种基于局部动态可重构(DPR)的新型可重构FFT处理器.相比传统的FFT设计,该设计方法在重构时间上得到了很大改进,同时,处理器能够动态地添加或移除重构单元.采用新颖的FFT控制算法,使得可重构部分面积很小.该处理器结构在Xilinx Viirtex2p系列FPGA上进行了综合及后仿真.较之Xilinx IPcore,其运算效率明显提高,而且还实现了IP核所不具备的动态可重构性.