Design and test methodology for an analog-to-digital convertermultichip module for experimental all-digital radar receiver operatingat 2 gigasamples/s

In this paper, we describe the development of an analog-to-digital (A/D) converter subsystem, based on a monolithic A/D converter chip, a demultiplexer chip, and a laminate multichip module, for an experimental all-digital receiver for an airborne radar. The evolution of techniques for recording and analyzing all the data from the assembled multichip module at the full sample rate of the A/D converter, and the ways in which this test data can be used to analyze the performance of A/D converters, are described. The problems which arise in the testing of GHz A/D converters, a number of which are unique to A/D conversion at such high sample rates, are pointed out. Finally, comments on future directions in the test of high performance A/D converters are presented     

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。     

串行输出A／D转换器的测试方法

以ＳＡＤ０８３２８位串行输出Ａ．Ｄ转换器为例，验证了一种串行输出Ａ／Ｄ转换器的特殊测试方法。详细介绍了诸如转换精度，三态特性等主要参数的测试方法和测试线路。测试结果表明，该测试方法完全满足串行输出Ａ／Ｄ转换器的测试精度要求。     

Design of A/D converters with hierarchic networks

A methodology for designing analog to digital (A/D) converters based on a hierarchic network is explored. The principle of this methodology and design procedure are presented. The characteristics and performances of the converter are compared with the converter based on the Hopfield network. Two circuit models for the A/D converters are described in this paper. As a hierarchic network is used, the A/D converters designed have no local minima in their operation, With the method proposed in the paper, high bit number A/D converters can be easily designed, and the converters designed are fast in signal conversion and stable in operation     

A self-calibration method for fast high-resolution A/D and D/Aconverters

Monolithic analog-to-digital (A/D) and digital-to-analog (D/A) converters suffer from the limited accuracy of the available circuit compensators. A self-calibration method allows the correction of the linearity errors of binary-weighted current-source arrays commonly used in high-speed converters. To achieve high-calibration accuracy a modified dual-slope method is used. This makes it possible to implement A/D and D/A converters with a resolution of 14 b or more at a conversion time of less than 15 μs     

D/A conversion interface design for DMT-ADSL applications

For high-speed internet access, high-performance analog front-ends are needed, and data converters are one of the crucial building blocks in these bent-ends. In this article we will report on the modeling and design of a D/A conversion interface for a DMT (discrete multi tone)-based ADSL system that could be integrated into a complete CMOS analog front-end. We will discuss the DMT transmit spectrum and its impacts on data converters, we will focus on modeling and simulating of the whole D/A interface, and we will describe a test chip implemented in a 0.6 μm CMOS process     

Photonic A/D conversion using low-temperature-grown GaAs MSM switches integrated with Si-CMOS

By linking the unique capabilities of photonic devices with the signal processing power of electronics, photonically sampled analog-to-digital (A/D) conversion systems have demonstrated the potential for superior performance over all-electrical A/D conversion systems. We adopt a photonic A/D conversion scheme using low-temperature (LT)-grown GaAs metal-semiconductor-metal (MSM) photoconductive switches integrated with Si-CMOS A/D converters. The large bandwidth of the LT GaAs switches and the low timing jitter and short width of mode-locked laser pulses are combined to accurately sample input frequencies up to several tens of gigahertz. CMOS A/D converters perform back-end digitization, and time-interleaving is used to increase the total sampling rate of the system. In this paper, we outline the development of this system, from optimization of the LT GaAs material, speed and responsivity measurements of the switches, bandwidth and linearity characterization of the first-stage optoelectronic sample-and-hold, to integration of the switches with CMOS chips. As a final proof-of-principle demonstration, a two-channel system was fabricated with LT GaAs MSM switches flip-chip bonded to CMOS A/D converters. When operated at an aggregate sampling rate of 160 megasamples/s, the prototype system exhibits /spl sim/3.5 effective number of bits (ENOB) of resolution for input signals up to 40 GHz.     

A/D转换器非线性特性简易测试方法

A／D转换器非线性测试是A／D转换器静态特性测试的一项重要内容。相对于以往成本较高的测试方法，文章提出了一种简易可行的测试方法：利用高精度D／A转换器和低精度A／D转换器的精度差，借助8051仿真系统进行测试。实验表明，该方法成本低廉，操作简单，适用于A／D转换器非线性特性的初期评测。     

Effects of crosstalk in demultiplexers for photonicanalog-to-digital converters

Time interleaving of samples digitized by a parallel array of analog-to-digital (A/D) converters provides a means of increasing the sampling rate beyond that possible with a single A/D converter. For time-interleaved photonic A/D converters, optical demultiplexers can be used to advantage. Both time-division and wavelength-division demultiplexers must yield low crosstalk between the parallel output channels in order to yield accurate A/D conversion. An analysis predicts the level and form of the resulting errors. The analytical results compare well with experiment     

A/D转换技术的应用与发展

首先分别介绍了当前六大模数转换技术的工作原理、电路结构、性能特点及应用领域,通过从转换速率、转换精度、分辨率、功耗、价格、面积等指标进行分析,将物理结构的设计与实际性能结合比较,总结出各自适合的应用领域.然后,根据对现有模数转换技术特点的分析及实际应用中对模数转换器性能的要求,对当前A/D转换技术向着高性能、低功耗、结构简单方向发展的趋势进行了预测.     

A noise-shaping coder topology for 15+ bit converters

A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3-μm CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate     

An overview of sigma-delta converters

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described     

A behavioral model of A/D converters using a mixed-mode simulator

A mixed-mode behavioral model of analog-to-digital (A/D) converters is described. A generalized model structure is introduced. The basic function of an A/D converter is to convert an analog voltage into a digital code, for example, a binary number. Three conversion methods (successive approximation, flash, and dual integration) which are commonly used in A/D converters are modeled and can be selected simply by specifying a parameter of the model. For brevity, only the successive-approximation method is described. The modeling considerations of various parts in the A/D converter, including the input amplifier, D/A converter, comparator, and the synchronization problem, are described. The model has been implemented in the Saber mixed-mode simulator. Simulation results are given     

Multibit oversampled ΣΔ A/D converters as front end forCD players

A technique is presented for deriving all of the different control signals needed for focusing and radial tracking in a digital servosystem for compact disc (CD) players, as well as the full band data from the disc. Because of the different natures of all those signals, different bandwidth and dynamic range, complex analog anti-aliasing circuits, and several types of A/D (analog-to-digital) converters would normally be required to convert the signals from the analog to digital domain. With the proposed technique it is possible to carry out the conversion of the high-frequency data as well as the low-frequency control signals with only a single type of multibit sigma-delta (ΣΔ) A/D converter in combination with digital signal processing. The use of ΣΔ type A/D conversion also has other advantages such as its suitability for integration in a CMOS VLSI process and the fact that the requirements for the anti-aliasing filters in front of the converters are relaxed due to the oversampling technique     

Time interleaved optical sampling for ultra-high speed A/Dconversion

A scheme is proposed for increasing the sampling rate of analogue-to-digital conversion by more than an order of magnitude by combining state-of-the-art A/D converters with photonic technology. Ultra-high speed sampling is performed optically by a multiwavelength pulse train. Wavelength demultiplexers convert the high repetition rate data stream of samples into parallel data streams that can be handled by available electronic A/D converters     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

Weighted median filters with sigma-delta modulation encoding

Digital decimation filters play a fundamental role in oversampled sigma-delta A/D decoders. In this paper, we first show that weighted median (WM) filtering of a demodulated sequence (at the Nyquist rate) can be implemented concurrently in the A/D decoder. Through a simple modification of the binary time-series outputted by the A/D modulator, the sequence obtained after the sigma-delta modulation (SDM) decoder is shown to be equivalent to WM filtering the multilevel sequence at the Nyquist rate. Second, we show that WM filters can be used for SDM decimation filters and that these filters are readily implemented in the SDM binary domain. A very promising characteristic of SDM converters equipped with WM decimating filters is that sharp discontinuities (edges) can be preserved and acquired. Thus, the bandlimited constraint imposed on the input signals can be relaxed making SDM more attractive to A/D conversion of signals containing sharp transitions. The proposed signal processing algorithms, in essence, combine A/D sigma-delta converters and WM filters into a single programmable system     

Linearity Testing of A/D Converters Using Selective Code Measurement

Measurement of integral non-linearity (INL) and differential non-linearity (DNL) of an A/D converter using the histogram method incurs large test time. This test time can be a significant percentage of the total test time, especially for high resolution and low sampling-speed A/D converters. This paper describes a test methodology for measuring the INL and DNL specifications of A/D converters by measuring a subset of the total set of code widths. This methodology is based on the fact that manufacturing variations in the electronic components of an A/D converter affect specific sets of codes in a similar manner. The proposed methodology measures code width parameters across such different sets of codes and estimates the A/D converter transfer function from the resulting information. A novel test generation methodology is presented for measuring the relevant code widths using a piecewise linear ramp that is designed to extract test information accurately from test data in minimal test time. The test procedure has been applied to different A/D converters and test time reduction of more than 75% has been achieved.

Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f _sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.     

An automatic error cancellation technique for higher accuracy A/D converters

An automatic error cancellation technique for higher accuracy successive-approximation analog/digital (A/D) converters is described. The technique uses a binary-weighted capacitor array as its own reference, and no other special elements are required for capacitor mismatch compensation. Experimental results indicate that more than 14-bit A/D conversion can be performed on a conventional MOS IC chip without trimming.