极细沟道NMOSFET中的大幅度随机电报信号噪声

研究了极细沟道NMOSFET器件的随机电报信号噪声(RTS)的特征.首次在室温下观测到了大幅度(大于60%)的RTS,发现当器件工作在弱反型区时,RTS幅度基本与温度和栅压无关.对RTS的动力学机制的分析及数值模拟表明,载流子数涨落与迁移率涨落引起的RTS的幅度随着沟道宽度的减小而增加,当沟道宽度减小至40nm以下时,由荷电陷阱对沟道载流子散射而产生的迁移率涨落对细沟道中RTS幅度的影响起主导作用.     

MOSFET中大幅度随机电报信号噪声的动力学特性

对 MOSFET器件的随机电报信号噪声 ( RTS)的特征进行了研究。室温下在极细沟道样品中观测到了大幅度 (大于 60 % )的 RTS,通过测量 RTS的俘获时间和发射时间与栅压和温度的依赖关系 ,获得了氧化层陷阱的位置与能级 ,证实了氧化层陷阱的热激活模型在细沟道 n MOSFET中仍然成立。同时发现当器件工作在弱反型区时 ,RTS幅度基本与栅压无关。对 RTS的动力学机制的分析及数值模拟表明 ,当沟道宽度减小至 4 0 nm以下时 ,由荷电陷阱对沟道载流子散射而产生的迁移率涨落对 RTS的幅度的影响起主导作用。     

基于能带计算的纳米尺度MOS器件模拟

随着器件沟道长度的不断缩小,多栅结构(包括FinFET)被普遍认为是有效改进Ion/Ioff的手段.量子力学效应对MOSFET中载流子分布和输运的影响已被认识和研究多年.在沟道截面被局限在数纳米量级时,一个更基本的固体物理问题,即能带或电子结构对材料几何尺寸的依赖性,逐渐显现出来并对器件特性产生不可忽略的影响.本文讨论如何从第一原理出发,高效率地计算沟道区的能带结构.在得到载流子的输运参数(有效质量、迁移率等)的基础上,通过直接求解带开放边界条件的薛定谔方程以得到器件的电学特性.考虑到应力对能带结构和散射机制的影响,还研究了载流子迁移率与晶向的关系.     

基于能带计算的纳米尺度MOS器件模拟

随着器件沟道长度的不断缩小,多栅结构(包括FinFET)被普遍认为是有效改进Ion/Ioff的手段.量子力学效应对MOSFET中载流子分布和输运的影响已被认识和研究多年.在沟道截面被局限在数纳米量级时,一个更基本的固体物理问题,即能带或电子结构对材料几何尺寸的依赖性,逐渐显现出来并对器件特性产生不可忽略的影响.本文讨论如何从第一原理出发,高效率地计算沟道区的能带结构.在得到载流子的输运参数(有效质量、迁移率等)的基础上,通过直接求解带开放边界条件的薛定谔方程以得到器件的电学特性.考虑到应力对能带结构和散射机制的影响,还研究了载流子迁移率与晶向的关系.     

栅宽对AlGaN/GaN HEMTs亚阈值摆幅的影响

制备了不同栅极宽度的AlGaN/GaN高电子迁移率晶体管，通过测量各器件电容-电压曲线和转移特性曲线，得到了栅沟道载流子输运特性以及亚阈值摆幅，结果显示当栅极宽度从10μm增加到50μm时，亚阈值摆幅下降了40.3%.定性且定量地分析了亚阈值摆幅值随栅极宽度变化的原因，发现不同的栅极宽度对应不同的极化散射强度，亚阈值摆幅的变化是由栅沟道载流子输运特性和极化散射效应造成的.为AlGaN/GaN高电子迁移率晶体管开关性能优化提供了新的视角与维度，将促进其更好地应用于无线通信、电力传输以及国防军工领域.     

GaN n-MOSFET反型沟道电子迁移率模型

在器件物理的基础上,提出了一种半经验的GaN n-MOSFET反型沟道电子迁移率模型.该模型考虑了位错、界面态、光学声子、离化杂质、表面粗糙、声学声子,以及高场对迁移率的影响.模拟结果表明,界面态和位错是影响沟道迁移率的主要因素,尤其是界面态,它决定了迁移率的最大值,而位错密度的增加使迁移率减小.此外,表面粗糙散射和高场散射主要影响高场下载流子迁移率.由此可见,GaN n-MOSFET沟道迁移率的提高依赖于晶体质量和界面质量的提高.     

SiO_2/SiC界面陷阱对SiC MOSFET开关损耗的影响

位于SiO_2/SiC界面处密度较高的陷阱,不仅俘获SiC MOSFET沟道中的载流子,而且对沟道中的载流子形成散射、降低载流子的迁移率,因而严重影响了SiC MOSFET的开关特性。目前商业化的半导体器件仿真软件中迁移率模型是基于Si器件开发,不能体现SiO_2/SiC界面处的陷阱对沟道中载流子的散射作用。通过引入能正确反映界面陷阱对载流子作用的迁移率模型,利用半导体器件仿真软件研究了界面陷阱对SiC MOSFET动态特性的影响。结果表明,随着界面陷阱密度的增加,SiC MOSFET开通过程变慢,开通损耗增加,而关断过程加快,关断损耗减小;但是由于沟道载流子数量的减少、导通电阻的增加,总损耗是随着界面陷阱密度的增加而增加。     

耗尽型4H-SiC埋沟MOSFET器件解析模型研究

建立了基于漂移扩散理论的4H-SiC埋沟MOSFET器件的物理解析模型。SiC/SiO_2界面处的界面态密度及各种散射机制都会导致器件载流子迁移率的下降,采用平均迁移率模型,分析散射机制对载流子迁移率的影响,讨论了界面态对阈值电压的影响。考虑到器件处在不同工作模式下,沟道电容会随栅压的变化而改变,采用了平均电容概念。器件仿真结果表明:界面态的存在导致漏极电流减小;采用平均迁移率模型得到的计算结果与实验测试结果较为一致。     

不同沟道长度对n沟MOSFET退化特性的影响

研究不同沟道长度n 沟道MOS场效应晶体管的热载流子效应对其退化特性的影响.实验结果表明,随着器件沟道长度的减小,其跨导退化明显加快,特别是当沟道长度小于1mm时更是如此.这些结果可以用热载流子注入后界面态密度增加来解释.     

MOSFET 1/f噪声的相关积分分析方法

文章将相关积分方法用于MOSFET 1/f噪声分析,发现器件的1/f噪声与RTS叠加模型产生的1/f噪声相关积分极其相似.通过对MOSFET噪声物理模型的分析和讨论,证明n-MOSFET的1/f噪声以载流子数涨落模型为主,p-MOSFET的1/f噪声以迁移率涨落模型为主结论的正确性.研究表明,相关积分方法可用于鉴别电子器件测量噪声所属的模型类型.     

Channel length dependence of random telegraph signal in sub-micronMOSFET's

The channel length dependence of the random telegraph signal (RTS) in a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been investigated both theoretically and experimentally. The key result is that, for a given surface potential, the RTS amplitude is proportional to 1/L², where L is the channel length, provided the contribution of the mobility fluctuation is much smaller than that of the carrier number fluctuation. A special test structure, consisting of a series combination of MOSFET's, is used to experimentally determine this channel length dependence, and good agreement with our simple theory is obtained     

RTS noise due to lateral isolation related defects in submicron nMOSFETs

The results of a systematic study of the random telegraph signal (RTS) fluctuations in submicron W-array n metal-oxide semiconductor field-effect transistors (nMOSFETs) are presented and analysed. These results include the dependency of the RTS amplitude and of the capture and emission time constants, measured both in the standard transistor and in the diode configuration, on the gate, drain and substrate voltage. For the latter configuration, the drain-substrate (or source-substrate) diode of the transistor is forward biased. Application of this technique for measuring RTS noise allows us to distinguish the drain (source) traps from the well-known channel traps. It is found that besides the classical channel-related RTSs, another type occurs which is associated with lateral isolation related (or edge-related) oxide defects, located near the drain or the source contact. As will be shown, the coulomb blockade significantly affects the capture and emission kinetics of these defects. The specific properties of such RTSs are studied in detail, as they may reveal useful information on their identification.     

Gate length effect on the RTS noise amplitude in SOI MOSFETs

The Random Telegraph Signal (RTS) noise amplitude in Silicon-on-Insulator MOSFETs is studied as a function of the gate length, by adding a second transistor in series. Different types of behavior can be distinguished, pointing toward a different origin of the related trapping centers. It is shown that in linear operation, the RTS amplitude and the corresponding low-frequency noise peak magnitude normally scales with 1/L. However, an increase with device length can also be found when the noise peaks of two RTSs add up. For RTSs occurring in the saturation regime, a complete elimination is observed for larger Ls, in support of the supposed film-related origin     

The gate bias and geometry dependence of random telegraph signalamplitudes [MOSFET]

A new random telegraph signal (RTS) amplitude model based upon band bending fluctuations has been developed, in contrast to other studies of RTS noise amplitudes, which are derived from RTS fitting parameters, it is demonstrated in this work that noise amplitudes may be predicted from band bending calculations and device DC characteristics. This new model suggests that the decrease in band bending associated with slow-state trapping results in mobility degradation for low gate biases (Coulombic-scattering-limited) and an enhancement in mobility due to vertical field reductions at high gate biases (surface roughness/phonon scattering limited). The band bending formulation shows good correlation with experimental data and accurately predicts the observed dependence upon effective channel length and width     

Hot-carrier stress effects on the amplitude of Random Telegraph Signals in small area Si p-MOSFETS

This paper studies the effect of avalanche hot-carrier (HC) stress on the amplitude of pre-existing Random Telegraph Signals (RTSs) in small area Si p-MOSFETs. It is shown that the RTS amplitude of a particular oxide trap increases after HC stress, both in linear operation and in saturation. From this, it is concluded that the effect of such a trap on the carrier transport in a small area MOSFET is also determined by the charges present at the interface and in the oxide. The impact of the observations on the RTS based modeling of flicker noise in MOSFETs will be briefly addressed.     

Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems

Increasing soft error rates for semiconductor devices manufactured in later technologies enforce the usage of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). As RRC introduces time overhead that increases the completion (execution) time, time constraints (deadlines) might be violated. This is a drawback for a class of computer systems where the correct operation is defined not only by providing the correct outcome of an operation but also by ensuring that the deadlines are met. These computer systems are referred to as real-time systems (RTSs). In general RTSs are classified as soft and hard RTSs depending on the consequences of violating the deadlines. For soft RTSs, where consequences of violating the deadlines are not very severe, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time (AET) is minimal. While minimal AET is important for soft RTSs, it is more important to provide a high probability that deadlines are met for hard RTSs, where consequences of violating the deadlines may be catastrophic. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. Traditionally, AET analysis have been used for soft RTSs and worst case execution time (WCET) analysis along with schedule feasibility have been used for hard RTSs. In this paper we introduce a reliability metric, Level of Confidence (LoC), which is equally applicable to both soft and hard RTS. LoC is used as a metric to evaluate to what extent a deadline is met. The main contributions of this paper are as follows. First, we present a mathematical framework for the evaluation of LoC when RRC is employed. Second, we provide a proof to verify the correctness of the proposed expression. Third, in the context of hard RTSs, we provide a method to obtain the optimal number of checkpoints that maximizes the LoC. Fourth, in the context of soft RTSs where the maximal LoC may not be needed, but instead some LoC requirement is needed, we present an optimization method for RRC that finds the number of checkpoints that results in the minimal completion time while the minimal completion time satisfies a given LoC requirement. Fifth, we use the proposed framework to evaluate and compare probabilistic guarantees when RRC is optimized towards soft RTSs.     

Random telegraph noise of deep-submicrometer MOSFETs

The random telegraph noise exhibited by deep-submicrometer MOSFETs with very small channel area (⩽1 μm²) at room temperature is studied. Analysis of the amplitude of the current fluctuations reveals that the trapped charges generate noise through modulation of the carrier mobility in addition to the carrier number. Parameters needed for modeling the carrier mobility fluctuation effect on the flicker noise in conventional MOSFETs are extracted directly from the random telegraph noise data     

Random telegraph signals in deep submicron n-MOSFET's

Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO₂ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel     

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.