埋沟CCD器件电荷处理容量的二维数值模拟

借助于二维器件模拟软件PISCES-IIB,通过在某相CCD电极下的耗尽区注入数量可控的电子电荷,对埋沟CCD器件电荷容量进行了定量分析。采用此方法对一种沟道宽度为7μm的CCD信道电荷容量进行了瞬态模拟,对不同结深、不同沟道掺杂浓度对CCD电荷容量的影响进行了讨论。得到了此结构工艺参数的初步优化结果,即CCD沟道表面掺杂浓度为结深为1 μm时,埋沟CCD的电荷容量可达文章提出的方法适用于其他CCD单元结构电荷容量的模拟。     

Two-dimensional transient analysis of a buried-channel charge-coupled device

An effective method of two-dimensional transient analysis of potential and charge carrier distribution in a buried-channel charge-coupled device (BCCD) operating in storage and transfer modes has been developed with the aid of the finite Fourier transform (FET) technique.The effect of different clocking schemes on charge carrier transfer inefficiency and charge handling capacity are examined and discussed using the method developed. It is also shown that, for a BCCD operating in the storage mode, two-dimensional analysis indicates that the charge handling capacity determined by one-dimensional analysis can result in overestimation, which is misleading.     

One-dimensional study of buried-channel charge-coupled devices

An analysis leading to some basic relations is performed on a one-dimensional model of a buried-channel charge-coupled device (CCD). Expressions for the charge distribution, potential, channel thickness, and location are obtained. These enable the effects of varying the device structural parameters, as well as the gate voltage and signal charge, to be examined very simply. The maximum charge-carrying capacity is discussed and compared to that for a surface-type CCD. Furthermore, the analysis is extended to a device with a nonuniformly doped semiconductor layer.     

Enhanced capacity CCD

This paper introduces a method for enhancing the charge capacity and lowering the leakage current in CCD's. The two-phase coplanar electrode structure is chosen as a vehicle for demonstrating the concept. The charge capacity enhancement is achieved by a combination of p-type and n-type implantations. This method of charge capacity enhancement relies on the increase of depletion capacitance in the storage well region of the CCD, as contrasted with other methods which increase the surface potential swing. A charge capacity analysis is undertaken and design constraints to provide maximum charge capacity are described. Results of measurements on the first test structure show 25-50-percent increase in charge capacity for buried-channel CCD's and 66-166-percent increase in charge capacity for surface-channel CCD's. A 2X-8X reduction in leakage current has been observed in these CCD's. The increased capacity and decreased leakage current should result in improved performance of CCD's in memory, signal processing, and imaging applications.     

A CPD image sensor with buried-channel priming couplers

A 398 (H) × 496 (V)-element CPD image sensor with buried-channel charge-priming-transfer (CPT) couplers for ⅔-in format has been developed. The buried-channel CPT structures by use of the external bias change has been adopted based on the theoretical consideration to suppress random noise and to improve vertical transfer efficiency for small signal charge. The vertical transfer efficiency even for small signal charges was improved up from 70 to 95 percent or more by use of the external bias charge in addition to priming charge. It was found that total random noise in the new image sensor corresponds to ∼ 400 electrons, which is about half of that in a conventional CPD image sensor with surface-channel CPT couplers.     

CCD图像传感器输出节点电荷容量设计

从电荷耦合器件(CCD)的满阱电荷容量和片上放大器的工作电压范围两个方面对器件的节点电荷容量进行了设计,并推导出输出节点电荷容量设计的优化公式。从公式中可以看出,输出节点的电荷容量设计除了需要满足CCD信号电荷转移本身所需的容量值以外,还必须保证节点处的电压变化范围在输出放大器线性工作区域内,才能使信号电荷能够完整线性地被放大器输出,从而保证CCD器件整体的非线性和满阱容量性能。因此,输出节点电荷容量的设计除了需要考虑节点自身的电容外,还应综合考虑输出放大器相关MOS管的宽长比、阈值电压、工作电压等因素。     

A new accelerated transfer method for the CPD image sensor

A new charge transfer method for the CPD image sensor is proposed. In this method a high transfer speed is achieved with the use of an accelerated charge priming transfer (CPT) coupler, which consists of the array of the conventional CPT's and inverter amplifiers. This constitution strikingly increases the speed as well as the efficiency of the charge transfer from the vertical transport lines with large capacitance to the horizontal buried-channel charge-coupled (BCCD) shift register. Under a high transfer efficiency of more than 98 percent, a short transfer time less than 1 µs has been attained, independently of the signal charge magnitude.     

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.     

Potentials and fields in buried-channel CCD's: A two-dimensional analysis and design study

It is shown that the two-dimensional potential variation in buried-channel CCD's can be considered to arise from a number of linearly contributing components. The components arising from the lateral variation in the gate voltage, depletion charge, and signal charge are clearly identified. Both the one- and two-level insulator structures are considered, and it is shown that the two-level structure can be reduced to an equivalent one-level device thereby greatly simplifying the analysis. Simple solutions are obtained for the potential and field variations in the channel region of both types of structure for zero signal charge. From these results, device optimization procedures aimed at minimizing the transfer inefficiency are obtained and applied to one-and two-level CCD's.     

A general gate-current p-MOS lifetime prediction method applicableto different channel structures

A recently developed surface-channel p-MOS lifetime prediction technique based on injection gate charge is extended to buried-channel devices. It is shown that a more general form of the equation governing the degradation accurately describes the degradation behavior of both surface-channel and buried-channel transistors, indicating that the method has general applicability for p-channel transistors     

Channel potential and channel width in narrow buried-channel MOSFET's

A new method is described for determining the effective width over which incremental charge spreads in a narrow buried-channel transistor. The method is based on the transconductance in the buried-channel mode. Experimental results for effective widths and channel potential shifts are presented for MOSFET's with effective channel widths from 2 to 10 µm. Two-dimensional numerical calculations verify the experimental results.     

Experimental demonstration of a buried-channel charge-coupleddevice in 6H silicon carbide

Fundamental operation of the first buried-channel charge-coupled device (BCCD) in 6H-SiC is presented. The n-type buried-channel was formed by ion implantation of nitrogen, and a double level overlapping-polysilicon-gate process was adapted to the SiC MOS system. An electron mobility of 200 cm²/Vs was measured in the channel, which is doped 1.6×10¹⁷ cm^-3. An eight-stage, four-phase BCCD shift register was operated in the pseudo-two-phase configuration at room temperature. At 5.5 kHz, the charge transfer efficiency is greater than 99.4%     

A survey of high-density dynamic RAM cell concepts

The performance capabilities of a variety of dynamic RAM cell concepts proposed in recent years are compared to the industry standard one-transistor cell. The new concepts are divided into three categories. The lateral charge sensing cells such as the Charge-Coupled cell, Hi-C cell, Merged-Charge cell, and Stacked-Capacitor cell. Vertical cells such as VMOS, the Punchthrough Isolated, and the Buried-Bit-Line cell which make use of the third dimension to achieve higher density. The Stratified-Charge cell and Taper-Isolated cell use current sensing of a dynamic change in the threshold voltage of a buried-channel transistor. The various cells were fabricated and compared on the basis of signal size, leakage rates, packing density, and fabrication and operational complexity. An overall figure of merit for a dRAM cell is suggested which combines all three considerations. Based on the cell concepts reported to date and this figure of merit, the Stacked-Capacitor, VMOS, and Punchthrough-Isolated cells ate the most promising charge storage cells. The Taper-Isolated cell, however, is shown to have significant overall advantage compared to the charge storage cells.     

Experimental performance of the buried-channel acoustic charge transport device

High-speed electron transport is accomplished in a new type of buried-channel charge transfer device which is based on the nonlinear acoustoelectric interaction between large amplitude surface acoustic waves (SAW) and electrons in GaAs. The performance of the acoustic charge transport (ACT) device is enhanced by design improvements which provide precise channel definition and charge injection structures. A transfer efficiency in excess of 0.996 has been measured in an experimental device operating at the SAW clock frequency of 358 MHz.     

A new threshold-voltage model for small-geometry buried-channel MOSFETs

This paper presents an analytic model for the threshold voltage of small-geometry buried-channel MOSFETs, in which the implanted buried-channel profile is approximated by a step profile. Based on the energy-band diagram, the threshold voltage of a buried-channel MOSFET is derived, in which the flatband voltage is physically defined. Using a new charge-sharing scheme, the threshold-voltage model considering the short-channel effect is calculated analytically. Similarly, based on the charge-sharing scheme, the narrow-width effect considering the field implant encroachment under the bird's beak is calculated. Combining both short-channel and narrow-width effects, the threshold-voltage model for small-geometry buried-channel MOSFETs is developed. In order to test the validity of the model, the buried-channel MOSFETs were fabricated in a production line and the threshold voltages were measured. Comparisons between the measured threshold voltage and the present model have been made. It is shown that satisfactory agreement has been obtained for wide ranges of channel lengths, channel widths and applied back-gate biases.     

On the design of ion implanted buried channel charge coupled devices (BCCDs)

The allowable range for the channel dose of a buried channel CCD is obtained. The maximum charge handling capacity without surface trapping effect is found to depend on the channel dose and the substrate concentration. In the case of two phase buried channel CCDs, the barrier implant dose can be estimated depending on the charge storage capacity desired. The result is applicable to ion implanted shallow junction devices and can be extended to deeper junction epitaxial buried channel devices.     

An epitaxially-grown charge modulation device

A charge modulation device (CMD) has been fabricated in a p-type epitaxial layer grown from the buried-channel silicon region of a charge-coupled device (CCD). Construction of the CMD directly above the CCD buried-channel and over the oxidized CCD transfer gates lowers the effective sense capacitance while providing isolation of the CMD source/drain regions. Responsivity values of 28 and 66 μV/e for feedback and no feedback conditions, respectively, were measured dynamically on test devices. Input-referred noise values of approximately four electrons r.m.s. were calculated from noise spectral density measurements assuming a low-pass filter 3 dB cutoff frequency of 5 MHz and correlated double sampling     

Design tradeoffs between surface and buried-channel FET's

A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.     

A two-dimensional numerical approach to achieve a silicon BCCD celloptimal design

The single charge stored in a silicon buried-channel charge-coupled device (BCCD) is studied under different technological specification. The approach is to seek an accurate determination of this parameter by using a 2-D numerical device analysis program. The calculated data are compared to experimentally measured BCCD characteristics. These investigations have led to some trends for design optimization for designers whose main motivation is the scaling down of BCCDs     

Lateral motion of the inversion layer of MOS structures in regions of variable doping density and oxide thickness

We describe computational methods and a new experimental technique for directly measuring the lateral spread of gate-induced surface inversion into the birdsbeak region of LOCOS (local oxidation of silicon) isolation. This method is of general use for characterizing all MOS structures with lateral variations in substrate doping, fixed charge, and/or oxide thickness. The procedure is applied to buried-channel CCDs to determine the location of generation sites along the channel-stop sidewalls.