Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Thin active layer a-Si:H thin-film transistors

We show that hydrogenated amorphous silicon thin-film transistors (TFT's) with active layer thickness less than 50 nm have improved performance for display applications. Using two-dimensional (2-D) modeling, we find previously observed degradation for thin active layers is due to electric field effects in the contact regions of staggered inverted devices and affects only the saturation characteristics; linear region performance actually improves with decreasing thickness. We have fabricated devices with extremely thin active layer (10 nm), and indeed find excellent linear region characteristics. In addition, direct tunneling across the undoped regions at device contacts reduces electric field effects, resulting in excellent saturation region characteristics, and gate-induced channel accumulation reduces the Schottky barrier width at direct metal contacts so that even devices without doped contact regions (i.e., tunneling contacts) are possible     

Device analysis for a-Si:H thin-film transistors with organicpassivation layer

Two dimensional device analysis has been performed to explain the experimental drain current-gate voltage (I_D-V_GS) characteristics of hydrogenated amorphous silicon thin-film transistors with various passivation layers. The shift of the I_D-V_GS curve in the negative direction and the increase of S-factor (the inverse of subthreshold slope in logarithmic I_D-V_GS curve) can be explained well by introducing positive fixed charges and defect states in the back interface region. It was found that the positive fixed charge and the defect density of a-Si:H TFT with an organic passivation layer are higher than those of conventional a-Si:H TFT with a silicon-nitride (SiN_x) passivation layer. The simulation shows that the front and back interfaces interact and this explains why the passivation affects the device performance such as V_th and S-factor in a-Si:H TFTs     

Ion implanted contacts to a-Si:H thin-film transistors

Fabrication steps to improve ion implanted source-drain contacts to hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) have been determined. After establishing a contact performance baseline using devices made with Al/intrinsic a-Si:H contacts, improvements were made to the metal/a-Si:H contact scheme using unheated and heated implants, single- and double-level phosphorous implants, a buffered HF acid dip just prior to metal deposition, Al and Al-Si-Cu metallization schemes, and a post-metallization anneal.     

On the quality of contacts in a-Si:H staggered electrode thin-film transistors

Amorphous silicon thin-film field-effect transistors have been made with a staggered electrode structure. In this structure we distinguish two separate contributions to the total contact resistance, namely, the Al/a-Si:H barrier itself and the bulk resistance of the underlying a-Si:H layer. Concerning the first contribution it was found that a P-implantation forming n⁺regions followed by post-metallization annealing (PMA) at a moderate temperature of 200°C is very efficient in reducing the resistance of the Al contacts to negligibly small values. The second contribution, i.e., the bulk resistance, implies a variable series resistance in field-effect (FE) measurements. Thin-film transistors (TFT's) with different gate lengths were used for the first time to determine this residual series resistance Rres.     

Degradation of n-channel a-Si:H/nc-Si:H bilayer thin-film transistors under DC electrical stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN_x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress (V_G = 25 V, V_D = 0), (ii) on-state bias stress (V_G = 25 V, V_D = 20 V) and (iii) off-state bias stress (V_G = −25 V, V_D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.     

Stacked pentacene layer organic thin-film transistors with improvedcharacteristics

Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm²/V-s, on/off current ratio larger than 10⁸, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device     

High performance a-Si:H thin film transistors based on aluminum gate metallization

We present a systematic study of the sputter deposition conditions for aluminum thin films employed as gate metallization for high performance a-Si:H thin film transistors (TFTs). Here, we vary sputtering parameters such as deposition temperature, process pressure, and power, all of which have a strong bearing on the surface roughness of the film, including hillock generation induced by thermal processing. For example, at a low deposition temperature (30°C) and a low process pressure (5 mTorr), the surface roughness appeared to be significantly reduced. Transistors with gate metallization deposited under these conditions show a low leakage current (10 fA), an ON/OFF ratio better than 10⁸, and a mobility of 1.1 cm²/V s. In contrast, films deposited at 150°C and 10 mTorr, yield a degradation in mobility to 0.77 cm²/V s and an increase in leakage current to 1 pA, caused by the high interface roughness of the TFT channel due to hillock formation on the Al gate.     

An integrated photodetector-amplifier using a-Si p-i-n photodiodesand poly-Si thin-film transistors

The authors propose a photodetector-amplifier circuit consisting of a bridge photodetector circuit and a CMOS differential amplifier, both monolithically integrated on a transparent substrate. A test circuit was fabricated using a-Si p-i-n photodiodes and poly-Si thin-film transistors on a quartz substrate. A clear effect of the differential amplifier was demonstrated in the test circuit. It is shown that the circuit performance can be controlled by changing the bias current of the differential amplifier. With a relatively low bias current on the order of 10^-11 A, the circuit works digitally with output voltages either close to 0 V or V_DD. The power consumption of the circuit is approximately 60 μW, which is low enough for use in two-dimensional arrays     

Advances in mobility enhancement of ITZO thin-film transistors:a review

Indium-tin-zinc oxide(ITZO) thin-film transistor(TFT) technology holds promise for achieving high mobility and offers significant opportunities for commercialization. This paper provides a review of progress made in improving the mobility of ITZO TFTs. This paper begins by describing the development and current status of metal-oxide TFTs, and then goes on to explain the advantages of selecting ITZO as the TFT channel layer. The evaluation criteria for TFTs are subsequently introduced,and the rea...     

Influence of mechanical bending and temperature on the threshold voltage instability of a-Si:H thin-film transistors under electrical stress

This paper studies the electrical characteristics of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) under flat and bending situations after AC/DC stress at different temperatures. Stress temperature was varied from 77 K to 400 K, and threshold voltage shifts were extracted to analyze degradation mechanisms. It was found that high temperature and mechanical bending played important roles under AC stress, with an enhanced stress effect resulting in a more serious degradation. This study also discusses the dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress.     

High performance tetrathienoacene-DDP based polymer thin-film transistors using a photo-patternable epoxy gate insulating layer

High performance organic thin-film transistors (OTFTs) are fabricated on an epoxy based photo-patternable organic gate insulating layer (p-OGI) using a top contact thin-film transistor configuration. This negative tone p-OGI material is composed of an epoxy type polymer resin, a polymeric epoxy cross-linker, and a sulfonium photoacid generator (PAG). Features from p-OGI can be precisely patterned down to ∼3 μm via i-line photolithography. In order to evaluate the potential of this epoxy type resin as a gate insulator, we evaluated the dielectric properties of the p-OGI and its gate insulating performance upon fabricating solution processed OTFTs using an organic semiconductor (OSC), namely tetrathienoacene-DPP copolymer (PTDPPTFT4). Results show that the PTDPPTFT4 based OTFTs with this p-OGI exhibit field-effect mobilities up to 1 cm² V⁻¹ s⁻¹, indicating the potential of high performance solution processed OTFT based on an epoxy based p-OGI/OSC system.     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200 °C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.     

Thermal analysis of active layer in organic thin-film transistors

This paper reports on the direct thermal observation of the pentacene – based organic thin-film transistors (OTFTs) under the real operating conditions. Liquid crystal (LC) spreading method was utilized for the thermal investigation of an active layer of the OTFT package. Temperature variation in the OTFT package was recorded for the different input power and significant heat generation was observed in the confined active layer. Detailed thermal performance of the OTFT package was projected using a Computational Fluid Dynamics (CFD) method as well. It was shown that the driving of the OTFT package with the drain voltage of ?15 V resulted in the active layer temperature of about 53.2 °C. The result indicates that the device design with effective thermal dissipation is imperative for reliable operation of the OTFT package.     

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100°C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 μm. Predictions for a-Si:H TFT's scaled down to 1 μm are also provided. The model is suitable for use in device and circuit simulators     

High mobility poly-Ge thin-film transistors fabricated on flexible plastic substrates at temperatures below 130°C

Depletion-mode poly-Ge thin-film transistors (TFTs) with an effective hole mobility of 110 cm²/Vs and an ON/OFF ratio of 10⁴ have been fabricated on flexible polyethylene therephtalate (PET) substrates, taking advantage of a novel stress-assisted crystallization technique. Proper manipulation of an otherwise destructive mechanical stress leads to a drastic drop of crystallization temperature from 400°C to 130°C. External compressive stress is transferred to the Ge/PET interface by bending the flexible substrate inward, during the thermal post-treatment. Proper patterning of the a-Ge layer before thermomechanical post-treatment leads to a minimal crack density in the processed poly-Ge layer. Reduction in the crack density plays a crucial role in alleviating the stress-induced gate leakage current emanated from the crack traces propagating from the channel into the gate oxide.     

High field-effect mobility from poly(3-hexylthiophene) thin-film transistors by solvent–vapor-induced reflow

Room-temperature exposure of spin-coated poly(3-hexylthiophene) (P3HT) films to ortho-dichlorobenzene vapor increases the field-effect mobility of the P3HT organic thin-film transistors (OTFTs). The mobility increases moderately with unsaturated vapor exposure, owing to increased crystallinity of the P3HT films; on the other hand, the mobility increases abruptly with saturated vapor exposure, to 0.11 cm²/V s. The saturated vapor exposure causes the P3HT films to reflow, leaving in the active area approximately 2–3 P3HT monolayers whose molecular ordering is enhanced by the flow-generated shear against the gate dielectric. Although the reflowed OTFTs degrade in air much faster than do the non-reflowed OTFTs due to the susceptibility of the ultra-thin reflowed films, they become highly stable when encapsulated, obtaining a lifetime of more than 3000 h.