Punchthrough transient voltage suppressor for low-voltageelectronics

Transient voltage suppressors for electronic circuits with power supply voltage of 3.3 V or lower are urgently needed but unavailable due to excessive leakage of low-voltage reversed p-n diodes. We analyzed several candidate device structures by using two-dimensional device simulation. Adopting the punchthrough mechanism in an n⁺p⁺p^-n⁺ structure rather than the traditional avalanche mechanism in a p⁺n⁺ structure, we can achieve low standoff voltage with excellent performances in low leakage current, low capacitance, and low clamping voltage. The new device appears to be satisfactory for protecting future electronic systems with power supply voltage at least down to 1.5 V     

Process and device characterization of high voltage gallium arsenide P-i-N layers grown by an improved liquid phase epitaxy method

GaAs P-i-N layers with an i-region net doping of less than 10¹² cm⁻³ were grown on P⁺ and N⁺ substrates by a modified liquid phase epitaxy (LPE) method. Doping profiles and structural data obtained by varius characterization techniques are presented and discussed. A P⁺-P-i-N-N⁺ diode with a 25 μm-wide i-region exhibits a breakdown voltage of 1000 V, a t_rr of 50 ns, and reverse current densities (at V_R = 800 V) of − 3 × 10⁻⁶ A/cm² at 25°C and 10⁻² A/cm² at 260° C.     

On the behaviour of buried oxygen implanted layers in highly doped GaAs

Highly doped GaAs substrate material (doping level 10¹⁸ cm⁻³) has been implanted with 350 keV O⁺ ions with doses of 10¹⁴ – 10¹⁶ cm⁻² to produce high resistivity layers which are stable at high temperatures. LPE growth of flat GaAs epilayers onto the implanted wafers was achieved up to doses of about 1 × 10¹⁵ O⁺/cm² and 5 × 10¹⁵O⁺/cm² for RT and 200°C implants, respectively. N-o-n and p-o-n structures (o: oxygen implanted) were fabricated in which breakdown voltages of up to 15 V were obtained. Examples for application of this isolation technique are shown.     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

A measurement method of the injection dependence of theconductivity mobility in silicon

A new electrical method to measure the conductivity mobility as a function of the injection level is proposed in this paper. The measurement principle is based on the detection of the voltage drop appearing across a n⁺-n-n⁺ (p⁺-p-p⁺) structure when a current step is forced into it at a given injection level in the intermediate region. This is obtained by using a three-terminal test pattern consisting of p⁺ , n⁺ layers realized on top of a n-n⁺ (p-p ⁺) epitaxial wafer, where the p⁺-n-n⁺ (n⁺-p-p⁺) surface diode is forward biased to monitor the conductivity of the epilayer. The use of separate terminals for injection control and mobility measurement allows this technique to overcome some limitations presented by other electrical methods available in literature, Mobility values measured up to 2·10¹⁷ cm^-3 are in good agreement with those predicted by the Dorkel and Leturcq's model (1981)     

A study of residual stress distribution through the thickness of p+ silicon films [thermal oxidation effects]

The effect of thermal oxidation on the residual stress distribution throughout the thickness of heavily-boron-doped (p⁺ ) silicon films is studied. The deflection of p⁺ silicon cantilever beams due to residual stress variation throughout the film thickness is studied for as-diffused and thermally oxidized films. Cantilevers of as-diffused p⁺ silicon films display a positive curvature (or a negative bending moment), signified by bending up of the beams. Thermal oxidation of the films prior to cantilever fabrication by anisotropic etching modifies the residual stresses in the p⁺ film, specially in the near-surface region (i.e. the top 0.3 to 0.5 μm for the oxidation times used here), and can result in beams with a negative curvature even when the oxide is removed from the p⁺ silicon cantilever surface subsequent to cantilever fabrication     

Lateral tunneling transistors fabricated by plane-dependent Si-doping in nonplanar epitaxy on GaAs (311)A and (411)A substrates

We have demonstrated the lateral tunneling transistors on GaAs (311)A and (411)A patterned substrates by using the plane-dependent Si-doping technique. Lateral p⁺-n⁺ tunneling junctions are formed by growing heavily Si-doped layers on patterned substrates. Current—voltage curves for both transistors show gate-controlled negative differential resistance characteristics. Furthermore, the peak current density of the lateral tunneling diodes fabricated on the (311)A patterned substrates increases as buffer layer thickness is increased, and a typical peak current density of 58 A/cm² for p = 6 × 10¹⁹ cm⁻³ and n = 7 × 10¹⁸ cm⁻³ is obtained when the buffer layer thickness is 1.2 μm. This study shows that plane-dependent Si-doping in non-planar epitaxy is a promising technique for fabricating tunneling transistors.     

MBE grown n+-i-δ(p+)-i-n+GaAs V-groove barrier transistor

The three-terminal n⁺-i-δ(p⁺)-i-n⁺V-groove barrier transistor (VBT) has been successfully fabricated by molecular beam epitaxy (MBE). The base terminal is connected to the δ(p⁺), the thin p⁺layer, by depositing aluminum on the etched V-groove. The demonstrated device possesses high potential of ultra-high-frequency (f_{r} > 30-GHz), high-power, and low-noise capability due to carriers transporting by thermionic emission and being controlled by the base-emitter bias.     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

High-current-gain small-offset-voltage In0.49Ga0.51P/GaAs tunneling emitter bipolar transistors grown by gas sourcemolecular beam epitaxy

Different emitter size, self-aligned In_0.49Ga_0.51 P/GaAs tunneling emitter bipolar transistors (TEBTs) grown by gas source molecular beam epitaxy (GSMBE) with 100-Å barrier thickness and 1000-Å p⁺(1×10¹⁹ cm^-3) base have been fabricated and measured at room temperature. A small-signal current gain of 236 and a small common-emitter offset voltage of 40 mV were achieved without any grading. It is found that the emitter size effect on current gain was reduced by the use of a tunnel barrier. The current gain and the offset voltage obtained were the highest and lowest reported values to date, respectively, in InGaP/GaAs system heterojunction bipolar transistors (HBTs) or TEBTs with similar base dopings and thicknesses     

Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

We proposed a new bulk FinFET that has a p⁺/n⁺ poly-Si gate consists of p⁺ region near the source and n⁺ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n⁺ poly-Si gate length (L_s). For given gate length (L_gles50 nm) and fin body width (W_finles30 nm), L_s was designed to satisfy the I _off requirement (i.e., 1 fA) of DRAM cell. Optimum L_s /L_g of 30-nm device was ~0.4 at a W_fin of 10 nm and ~0.2 at a W_fin of 15 nm     

17.2-percent efficient (AMO) p+-i-n InP homojunction solar cells

p⁺-i-n junction structure InP solar cells have been fabricated on n-type substrates by the LPE method. The conversion efficiencies for the active area of this cell are as high as 21.5 percent at AM1.5 and 17.5 percent at AMO, respectively. These are the highest ever reported for InP. The radiation resistance to 1-MeV electrons can be improved by optimizing i-layer thickness to 1 µm. However, the radiation-resistance of the p⁺-i-n cell is not so good as the n⁺-p structure cell, because of the increase in the leakage current due to the recombination center introduced in the i-layer with irradiation.     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

A self-aligned short process for insulated-gate bipolar transistors

An n-channel vertical insulated-gate bipolar transistor (IGBT) process which implements a self-aligned p⁺ short inside the DMOS diffusion windows is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the p⁺ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGBTs when compared to conventional IGBTs with non-self-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing p⁺ diffusion depth and electron irradiation dosage, as well as with larger p⁺ diffusion windows     

20-GHz high-power GaAs DDR-IMPATT diodes with a p+-p-n-n+structure

GaAs DDR (double-drift-region)-IMPATT diodes have been made by using epitaxial wafers with a p⁺-p-n-n⁺structure, which was made by successive liquid-phase epitaxy of p⁺, p, and n layers on n⁺substrate in one heat cycle. On the diodes with copper heat sink, the maximum CW output power of 1.2 W was obtained at 21 GHz with the efficiency of 15.6 percent.     

Nickel ohmic contacts to p and n-type 4H-SiC

The first demonstration of Ni ohmic contacts to both p⁺ and n⁺ 4H-SiC formed by ion implantation is reported. Sample preparation conditions are described and experimental results presented. Specific contact resistances in the range of 10^-4 Ω cm ² and 10^-6 Ω cm² for p⁺ and n⁺ 4H-SiC, respectively, have been determined by the transfer length method     

Impact of Ge implantation on the electrical characteristics of TiSi2 p+/n shallow junctions with an a-Si (or apoly-Si) buffer layer

A new technology for forming a titanium-silicide shallow junction by combining germanium implantation with an amorphous-silicon (or a poly-silicon) buffer layer has been proposed for MOSFETs. The use of a buffer layer between Ti and Si can avoid the consumption of bulk-silicon and the recession of TiSi₂ film into the source/drain junctions during the silicidation process. In this study, the important role of germanium-implantation on the formation of TiSi₂ contacted p⁺/n junctions was examined. After subsequent implantation of Ge⁺ and B⁺ into the TiSi₂ film, samples were annealed at different temperatures to form p ⁺/n junctions and C54-TiSi₂. Since the penetration of titanium atoms was suppressed due to the germanium-implantation, the periphery leakage and the generation leakage were improved and TiSi₂/Si interfaces were even smooth. Therefore, p⁺/n junctions with a very low leakage current (0.192 nA/cm ² at -5 V) and an excellent forward ideality factor (n≈1.002) can be obtained. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth is 400