VLSI implementation of Reed-Solomon encoder algorithm for communication systems

Reed Solomon codes are used to identify and correct data errors in transmission and storage systems. In this paper we designed a compact RS(255, 223) encoder structure based on analysis of the Reed-Solomon (RS) coding theory used in deep space communications. The encoder is implemented with 32 optimized finite multipliers, of which the redundant operations are reduced to minimize the number of modulo 2 additions or XOR gates based on analyzing the structure of multipliers in RS encoder that are simple and can ensure high speed operations. The simulation results show that the designed structure has advantages such as high efficiency and low complexity ensuring good coding performance.     

An architecture for real-time multimedia communication systems

A multimedia communication system includes both the communication protocols used to transport the real-time data and the distributed computing system (DCS) within which any applications using the protocols must execute. The architecture presented attempts to integrate these communications protocols with the DCS in a smooth fashion in order to ease the writing of multimedia applications. Two issues are identified as being essential to the success of this integration: the synchronization of related real-time data streams, and the management of heterogeneous multimedia hardware. The synchronization problem is tackled by defining explicit synchronization properties at the presentation level and by providing control and synchronization operations within the DCS which operate in terms of these properties. The heterogeneity problems are addressed by separating the data transport semantics (protocols themselves) from the control semantics (protocol interfaces)     

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-μm VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology     

VLSI designer's interface

This presentation discusses the availability of a standard-cell library targeting the TSMC-0.25 μm, 2.5 V CMOS process; IBM's development of a new "Double-Gate" transistor fabricated in an SOI process and Intel's "TetraHertz Transistor," which it claims is the world's smallest transistor with a gate length of only 15 nm; Modu-Lab, a Web site dedicated to illustrating microfabrication techniques for the basic process steps of deposit, pattern, etch, and repeat; OpenCores' free open-source 33/66 MHz 32-bit PCI Bridge Soft Core, a complete synthesizable RTL (Verilog) code that provides bridging between the PCI and a WISHBONE (system-on-chip) bus; Foveon's development of a full-color image sensor chip that uses three layers of photodetectors embedded in silicon; Aldec and Synplicity design entry and simulation tools for universities and students; a new set of system-on-chip test benchmark circuits; and takes a look at nanotechnology initiatives     

高速光通信中的级联码设计与VLSI实现

本文设计了应用于光通信系统的RS(255,239)+BCH(2184,2040)级联码编解码电路。级联码系统中,RS码与BCH码速度的不匹配是影响性能的最大瓶颈,本文采用并行度为8的并行BCH编解码器来实现与RS码速度的匹配。推导了BCH编码器并行化方法,并利用子项共享的方法来减少子项的扇出,使每个子项的最大扇出数不超过10。利用并行伴随式计算和并行钱氏搜索来提高BCH译码器的吞吐量,同时充分利用截短码的特性使钱氏搜索时间减少了46%。级联码的编解码器已用TSMC 0.18-μmCMOS标准单元库方法实现,后仿真结果表明,在312.5MHz的时钟下,级联码能够正常工作,能实现2.5Gb/s的数据吞吐量。建立了基于Xilinx FPGA的测试验证平台,测试结果表明电路功能正确、工作正常。     

Self-reconfiguration of real-time communication in cyber-physical systems

Today, in domains like automation and robotics systems consist of various sensors and computation nodes. Due to the temporal dependency in quality of measured data, such Cyber-Physical Systems (CPS) commonly have real-time requirements on communication. In addition, these systems shall become more flexible and scalable, e.g., by adding new components to the CPS. This would be most suitable if a CPS could react to the presence of a new component and reconfigure itself to run afterward with the new component integrated to the CPS. This capability is covered by the term Plug-and-Produce. In this paper, we propose a concept to enable Plug-and-Produce within a CPS whose network uses different communication media, e.g., Ethernet and CAN. To enable real-time communication provided by different communication protocols, their different synchronization mechanisms have to be combined to get a common time base within the entire system. For this purpose, we consider Ethernet as well as CAN-based real-time communication protocols and their synchronization mechanisms. The proposed concept for self-reconfiguration aims to be integrated into our three layered software architecture that is presented as well.     

A multistage hierarchical distributed arbitration technique for priority-based real-time communication systems

ISO 11898 is a communication protocol based on the carrier sense multiple access with collision detection and arbitration on message priority (CSMA/CD+AMP) technique, which at present is largely used as a real-time network for industrial environments. Unfortunately, because of the peculiarities of the arbitration technique it adopts, it suffers from severe limitations on the maximum extension of the network, which cannot be overcome simply by means of improvements in the transceiver's technology as they depend on the limited propagation speed of the signals on the communication support. In this paper, a new kind of network is presented that features a behavior very similar to ISO 11898, but which achieves noticeably larger areas to be covered without having to reduce the bit rate. It relies on a tree topology and adopts a brand new multistage hierarchical distributed arbitration technique, which takes the increased propagation delays into account properly.     

Optical interconnections for VLSI systems

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.     

A VLSI for real-time linear operations and transforms

A VLSI system, utilizing 16 systolic array multipliers, designed to compute vector-matrix products at a rate of 640×10⁶ MACs is presented. The 448,000-transistor, 1.6-μm CMOS device incorporates a dual timing scheme which allows multiplexing of hardware units over identical operations. This hardware balances maximum internal operating frequency with external data bandwidth and results in an improved ration of the signal throughput to silicon area. This system has wide application because of its ability to compute correlation, convolution, linear transforms, and connections in multilayer perceptrons     

On the design of globally optimal communication strategies for real-time noisy communication systems with noisy feedback

A real-time communication system with noisy feedback is considered. The system consists of a Markov source, forward and backward discrete memoryless channels, and a receiver with limited memory. The receiver can send messages to the encoder over the backward noisy channel. The encoding at the encoder and the decoding, the feedback, and the memory update at the receiver must be done in real-time. A distortion metric that does not tolerate delays is given. The objective is to design an optimal real-time communication strategy, i.e., design optimal real-time encoding, decoding, feedback, and memory update strategies to minimize a total expected distortion over a finite horizon. This problem is formulated as a decentralized stochastic optimization problem and a methodology for its sequential decomposition is presented. This results in a set of nested optimality equations that can be used to sequentially determine optimal communication strategies. The methodology exponentially simplifies the search for determining an optimal real-time communication strategy.     

Resource partitioning for real-time communication

For real-time communication services to achieve widespread usage, it is important that network managers be allowed to control the services effectively. An important management capability concerns resource partitioning. Resource partitioning is useful for a number of applications, including the creation of virtual private subnetworks and of mechanisms for advance reservation of real-time network services, fast establishment of real-time connections, and mobile computing with real-time communication. In previous work, the authors presented a scheme for resource partitioning in a guaranteed performance networking environment with EDD-based packet scheduling disciplines. The present paper gives the results of research in resource partitioning, with admission control tests for resource partitioned servers for four representative scheduling disciplines, FIFO, WFQ, RCSP and EDD. The simulations confirm the intuition that resource fragmentation losses due to resource partitioning are small and that resource partitioning reduces the admission control computation overhead. An interesting result from the simulation experiments is that, under circumstances that arise naturally in multi-party communication scenarios, resource partitioning results in higher overall connection acceptance rate. The authors also present experiences with implementing resource partitioning in the second generation of Tenet real-time protocols; this implementation, with resource partitioned servers, runs on multiple platforms, including Sun workstations under SunOS, DEC workstations under Ultrix, and PCs under BSDI Unix