一种减小存储单元间串扰的新型阵列布局结构

针对SRAM阵列中的串扰,给出了一种新型布局结构,即字线的“错序译码”组织结构和位线的“间隔译码”组织结构．“错序译码”组织结构是根据程序“顺序局部性”的特点提出的,“间隔译码”组织结构是根据“串扰局部性”的特点提出的．在存储器单元比值一定的条件下,采用这种结构可以显著减小由寄生RC所带来的单元间的串扰,提高存储器读写的速度和工作可靠性．仿真结果进一步证实了这种结论．     

一种减小存储单元间串扰的新型阵列布局结构

针对SRAM阵列中的串扰,给出了一种新型布局结构,即字线的"错序译码"组织结构和位线的"间隔译码"组织结构."错序译码"组织结构是根据程序"顺序局部性"的特点提出的,"间隔译码"组织结构是根据"串扰局部性"的特点提出的.在存储器单元比值一定的条件下,采用这种结构可以显著减小由寄生RC所带来的单元间的串扰,提高存储器读写的速度和工作可靠性.仿真结果进一步证实了这种结论.     

基于信道传输矩阵逆矩阵减小微带线间串扰

针对现有串扰减小方法效果有限、成本高、资源消耗多等问题,提出了一种基于信道传输矩阵逆矩阵减小微带线间串扰的方法。该方法通过将信道传输矩阵化为单位阵来实现串扰减小。根据理论分析设计了该方法的电路结构。仿真结果表明,使用该方法进行串扰抵消后串扰幅度和抖动都有明显改善,且该方法的电路结构简单。     

柔性可延展电路中互连结构设计及布局优化

针对柔性可延展电路由于不合理的互连结构设计和布局而造成的串扰问题,提出一种基于响应面法对柔性可延展电路互连结构进行设计与布局的方法。以柔性可延展电路中的通用互连结构为研究对象,通过正交实验和方差分析,筛选出对串扰存在显著性影响的因素。基于正交设计分析结果,运用中心复合实验设计法获得样本数据,利用ANSYS Electronic Desktop获得串扰响应值,构建串扰与影响因子之间的二阶多项式响应面模型,以近端串扰和远端串扰之和的最小值为优化目标建立优化模型,通过优化算例验证了该方法的可行性,为可延展通用互连导线的优化与布局提供了参考依据。     

蛇形防护线降低非平行传输线中串扰的研究

非平行传输线之间的耦合(串扰)是非常复杂且难以预测的,但是在高速电路中,这种串扰影响又必须考虑在内.文中针对非平行传输线问题,在其间加入蛇形防护线以降低串扰,同时根据非平行结构的特殊性,又对蛇形防护线的一般结构进行改进,将非平行传输线单元下的规则蛇形线改用间隔较小的不规则蛇形线,并在蛇形线上加入短路过孔,以进一步减小远端串扰.结果表明,我们的设计能有效抑制线间的串扰,具有实际的应用价值.     

高精度光纤陀螺检测电路串扰自检测研究

光纤陀螺检测电路应用过程中,受到自检测方案的影响,导致串扰故障检测所需测试矢量较多。因此,提出高精度光纤陀螺检测电路串扰自检测研究。分析光纤陀螺数字闭环检测原理,并提取检测电路串扰特征。根据闭环电路的连续信号微分方程,计算等效模拟输入转速。结合数字阶梯波算法,设计电路串扰检测方案。再计算地球自转角速率的分量测量死区,得到电路串扰测量结果。仿真结果表明：所提出的串扰自检测方法,与嵌入式“反射器”的新型谐振陀螺仪和多导体传输线串扰不确定性问题的计算方法相比,当串扰故障覆盖率为80%,本文方法的矢量数量为46个,降低了自测试所需的成本。     

两相邻耦合RC互连的串扰效应及其抑制

随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。     

PCB设计中的串扰分析

串扰是高速电路实现其信号完整性的主要障碍之一,为了尽可能的地减小串扰对信号品质的影响,保证电路功能的高品质实现,有必要分析PCB设计中的串扰问题。本文针对一块板卡中,数据丢包的现象,利用理论分析和软件仿真的方法,得出串扰是数据品质不佳的罪魁祸首。并对串扰进行定量的分析,最后找到抑制串扰的方法,得到高品质的信号输出。     

非平行微带线间的串扰抵消研究

非平行微带线是印刷电路板(PCB)上不可避免的互连结构。针对PCB 上非平行微带线间的串扰问题,用平行微带线近似非平行微带线,把平行耦合微带线间的串扰抵消方法应用到非平行耦合微带线中,提出了利用耦合传输线信道传输矩阵方法来进行远端串扰抵消,在对非平行耦合传输线信道传输矩阵进行特征值分解的基础上构建串扰抵消电路。仿真了非平行微带线间夹角分别为q=3°、5°、10°时的串扰,结果表明,该方法可以有效改善非平行微带线上信号眼图的质量,串扰抵消效果良好。     

柔性可延展耦合电路互连结构频域与时域特性分析

串扰作为信号完整性的重要影响因素之一,在进行高速可延展电路设计时,需要对电路中互连结构之间的串扰进行分析,以验证结构的合理性。以耦合可延展通用互连结构为研究对象,在高速电路中运用有限元法对形变后的耦合可延展通用互连结构进行频域分析,研究了频率以及形变对电路中相邻导线间串扰产生的影响。利用频域分析得到的S参数建立时域分析的电路模型,对耦合可延展通用互连结构进行了时域分析,研究频率以及形变对导线端口输出电压产生的影响,对频域分析结果进行验证,为可延展柔性电路互连结构的设计提供了参考。     

基于异构忆阻器的1T2M多值存储交叉阵列设计

忆阻器作为一种新型电子元件,具有尺寸小、读写速度快、非易失性和易于与CMOS电路兼容等特性,是实现非易失性存储器最具发展前景的技术之一.但是已有的多值存储交叉阵列存在电路结构复杂、漏电流和存储密度低等问题,影响了多值存储交叉阵列的实用性.该文提出一种基于异构忆阻器的多值存储交叉阵列,其中存储单元由1个MOS管和两个具有...     

FIFO存储电路的设计与实现

文章介绍了一个正向设计，并已成功流片的FIFO存储器电路结构设计及关键技术．重点研究了实现该电路的两类关键技术，存储电路和控制逻辑。文中的设计思想和具体的逻辑电路可以通用于所有先进先出存储器的设计。     

无交叉效应无源OLED驱动电路的实现

从OLED的结构特性与发光原理出发，结合简单的电路模型和实验中观察到的现象分析了交叉效应的成因，提出了一种简单实用的驱动电路结构，利用反向电压抑制法有效地解决了无源OLED显示时的交叉效应问题，最后给出了对电路结构进行恒流源改进的设想。     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors

In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors. While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents a low area, performance and power dissipation penalty.     

OLED点阵驱动电路设计及OLED驱动特性研究

设计了一种方便测试OLED显示屏特性的驱动电路。用此驱动电路研究了与驱动方式相关的(OLED显示屏特性即“串扰”、老化、击穿等，观测到与OLED“形成过程”相对应的“恢复过程”。实验结果表明．通过对驱动电路采取适当的措施，能够减轻“串扰”和击穿对显示屏造成的影响，并延长显示屏的使用寿命。     

用液晶显示控制驱动器实现OLED的矩阵字符显示

本文介绍了用液晶显示控制驱动器实现有机发光二极管（OLED）的矩阵字符显示。通过对液晶显示控制驱动器的输出波形和行输出电路的改进，得到了适合OLED矩阵驱动的电路，实现了无交叉效应的OLED矩阵字符显示。     

交叉重组方法在帆板驱动线路中的应用研究

帆板驱动线路（SADE：Solar Array Drive Electronics）和电机绕组的连接通常是固定的,即驱动线路的主备份分别连接电机绕组的主备份.原理上看,主备份线路是相互独立的,但考虑主备份电机绕组是并绕模式,工作的电机绕组会通过电磁耦合施加电应力到非工作线路,从而对非通电器件产生应力冲击,影响整机性能.本文通过在驱动线路和绕组阀引入交叉重组设计,解决了主备份驱动线路之间的耦合影响,大大提高了可靠性.     

Cross‐talk Cancellation Algorithm for 3D Sound Reproduction

If the right and left signals of a binaural sound recording are reproduced through loudspeakers instead of a headphone, they are inevitably mixed during their transmission to the ears of the listener. This degrades the desired realism in the sound reproduction system, which is commonly called ‘cross‐talk.’ A ‘cross‐talk canceler’ that filters binaural signals before they are sent to the sound sources is needed to prevent cross‐talk. A cross‐talk canceler equalizes the resulting sound around the listener's ears as if the original binaural signal sound is reproduced next to the ears of listener. A cross‐talk canceler is also a solution to the problem—how binaural sound is distributed to more than 2 channels that drive sound sources. This paper presents an effective way of building a cross‐talk canceler in which geometric information, including locations of the listener and multiple loudspeakers, is divided into angular information and distance information. The presented method makes a database in an off‐line way using an adaptive filtering technique and Head Related Transfer Functions. Though the database is mainly concerned about the situation where loudspeakers are located on a standard radius from the listener, it can be used for general radius cases after a distance compensation process, which requires a small amount of computation. Issues related to inverting a system to build a cross‐talk canceler are discussed and numerical results explaining the preferred configuration of a sound reproduction system for stereo loudspeakers are presented.