Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated     

New tungsten silicide thin-film resistor technology applied to GaAs integrated circuits

Tungsten silicide resistors in the range 50?300 ? sheet resistance have been deposited on GaAs by RF sputtering and patterned by etching in an SF6 plasma. High-temperature stability has been demonstrated and a change in resistance of less than 01% after lOOOh at 125°C achieved with passivated resistors.     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

Microstructure and properties of multilayer-derived tungsten silicide

In metallization, peeling and oxidation of tungsten silicide are the most serious problems of tungsten rich silicide. In this study, multilayer-derived silicon rich tungsten silicide with the silicon film on the outermost surface is investigated to avoid these problems. The dependence of sheet resistance on the annealing conditions is studied. X-ray diffraction results indicate that silicide formation is nearly completed after 30 min annealing at 750° C. Microstructures of silicide and polycides are investigated by electron microscopy. Silicide deposited on SiO₂ has smaller grains that deposited on poly-Si. A resistivity of 60 μΩ-cm is obtained for multilayer-derived WSi_2.3.     

Electronic transport properties of tungsten silicide thin films

Tungsten suicide thin films have been prepared by neutralized ion beam sputtering of the metal onto a polycrystalline silicon layer followed by furnace annealing. The films appear to be essentially sing le-phase disilicide with thepossibility of a percent or so carbon and oxygen content. The material behaves as a classical metallic conductor, with a temperature-independent residual resistivity of 16 μΩ-cm and a room temperature intrinsic resistivity of 7 μΩ-cm. Hall effect measurements indicate the material is predominantly a hole conductor, with a room temperature Hall mobility of 30cm²/V^-s and an apparent free carrier concentration of 8.9×10²¹ cm⁻³. The effective one-carrier mobility derived from geometrical magnetoresistance data, on the other hand, is ≈95 cm²/V^-s; this difference, taken together with the effect of temperature on the transport properties, suggests there is mixed conduction.     

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi₂. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 μm. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule     

Thin silicide development for fully-depleted SOI CMOS technology

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10^-7Ω-cm ² is necessary for achieving low contact resistance in a sub-0.25-μm fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed     

Nickel silicide formation by electroless technique for ULSI technology

In this paper we report on the formation of nickel silicide by electroless process. The nickel plating solution was composed of a mixture of NiSO₄·6H₂O, NaH₂PO₂·H₂O, Na₃C₆H₅O₇, and NH₄Cl, where NiSO₄·6H₂O is the main nickel source and NaH₂PO₂·H₂O is the reducing agent. The nickel silicide formation was carried out by heating the deposited samples in vacuum at temperatures from 100 °C to 800 °C. The evolution of NiSi phase from the nickel film was verified using the X-ray diffraction technique and Raman spectroscopy. The surface morphology was studied using AFM technique. The electroless plating technique can provide a cheap and easy process for forming nickel silicide, and has potentiality of application for the electronic device industries.     

Conductivity changes in tungsten silicide films due to rapid thermal processing

Several limitations of the polysilicon gate in VLSI have led to the development of a silicide/polysilicon material as all alternative to polysilicon. Recently, rapid thermal processing has been investigated for annealing such polycide films. We report here the electrical-conductivity changes during the process of rapid thermal annealing in CVD tungsten silicide films. It is shown that electrical resistivity initially increases due to changes in the silicon to tungsten ratio and then drops to about one-tenth of the initial value, thus suggesting a minimum time and power required for achieving low-resistivity tungsten silicide films in VLSI interconnections.     

High-performance metal/silicide antifuse [for CMOS technology]

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Ω, which is a factor of 10 less than that of Si-based antifuses (poly/n⁺ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory     

State assignment of finite state machines for low powerapplications

The authors present an algorithm for the state assignment in finite state machines targeted for minimal switching power dissipation. The adjacent states are assigned codes closer in Hamming distance by our algorithm, which modifies the given state transition graph so that it can be embedded in an n-cube. Experimental results show that the switching activity obtained by the proposed method is better than the previous method     

Advanced tungsten plug process for beyond nanometer technology

This investigation elucidates various tungsten (W) nucleation layers in different W-plug fill processes. Four W-plug nucleation layers are evaluated. They involve an atomic layer deposition (ALD) W nucleation with SiH₄-base sequential nucleation layers, an ALD W nucleation with B₂H₆-base sequential nucleation layers, a conventional W chemical vapor deposition (CVD) nucleation layer, and a pulsed nucleation layer, respectively. Bulk deposition includes high pressures of 300 Torr and conventionally 90 Torr with hydrogen as a reductant of WF₆. A scanning electron microscopic analysis of the ALD W nucleation layer is conducted; it is a thin, smooth and dense film, which enhances the bulk deposition grain growth to increase grain size with low resistivity. Electrical results for ALD W processes are comparable to those for conventional W process in general barrier process condition. However, as the W-plug fills process on the weak and thin metal organic chemical vapor deposited (MOCVD) TiN barrier is varied, the ALD W processes retain their original electrical resistance performance. Unlike ALD W processes, the conventional W CVD suffers from serious contact resistance opening and tail bits. Transmission electron microscope profiles reveal that the thin and dense B₂H₆-base sequential nucleation layers prevent WF₆ molecular penetration through the TiN/Ti_x interface. Additionally, various W-plug fill processes are implemented in the tungsten damascene test vehicle, and the ALD B₂H₆-base sequential nucleation layers and subsequently formed bulk deposition at 300 Torr have lower resistance than under other conditions. The contact profile obtained using the transmission electron microscope reveals that the ALD B₂H₆-base W-plug has favorable fill-in capability for both 100 nm and 60 nm contact sizes. Their lower resistivity and thinner nucleation layer suit them in particular to implement at a contact size of 100 nm and smaller. The ALD B₂H₆-base sequential nucleation layers and subsequently formed bulk deposition at 300 Torr can be used in the next generation of W-plug fill process.     

Optimization of a self-aligned titanium silicide process forsubmicron technology

The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi ₂ layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n⁺ or n ⁺/p⁺ gate have demonstrated that the self-aligned process can be integrated in a 0.8-μm double-metal CMOS process     

适用于智能电池的微控制器存储器技术

大多数智能电池都要用到微控制器（MCU）。MCU的体系结构不但会影响电池本身的性能，甚至会间接影响到电池供电的设备。因此，设计人员在选择MCU时不能掉以轻心，必须要考虑到多方面的因素，像价格、处理速度、代码兼容性、可移植性，以及是否有实用的应用资料、在相关产品中的应用情况、开发环境的多寡都是决策时的重要依据。程序存储器的类型——如ROM，EPROM（可擦除可编程只读存储器）和Flash——也是要考虑的一个因素。对于某一类应用，各种存储器都有其优点和不足。显然，如果一个微控制器厂商的产品品种比较全，包含了各种类…     

MOSFET-based temperature sensor for standard BCD smart power technology

Two on-chip temperature sensors for smart power BCD technology were compared. Temperature sensors based on bipolar transistors failed when DMOS power transistors were working under AC conditions because of substrate-coupled effects. An alternative MOSFET-based temperature sensor derived from a supply-independent CMOS bias source may overcome the problems associated with BCD technology.     

灵巧结构与蒙皮中的光纤传感技术

在复合材料结构部件内或蒙皮中埋入光纤传感网络，称为灵巧结构与蒙皮。该技术受到各国政府和军方的高度重视，成为９０年代材料与传感技术的一个热点。     

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate     

An overview of smart power technology

The evolution of smart power technology and the impact of this technology on electronic systems are reviewed. After providing a definition of smart power technology, the author describes the key technological developments in power semiconductor devices, namely power MOSFETs and IGBTs (insulated-gate bipolar transistors). These developments are the foundation upon which smart power technology rests. Smart power technology requires the marriage of power device technology with CMOS logic and bipolar analog circuits. The technical challenges involved in combining power handling capability with on-chip regulation of overcurrent, overvoltage, and overtemperature conditions are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies     

Experimental study of AlGaAs/GaAs HBT device design for powerapplications

An experimental study of AlGaAs/GaAs heterojunction bipolar transistor (HBT) device design for optimizing key DC and RF performance parameters relevant to power device applications is reported. The design of the collector, base, and base-emitter junction is investigated for improved power device performance, and novel device structures are presented. Device scaling effects and the extent to which air-bridged interconnect can reduce parasitics in large power devices are also explored. Power HBTs employing some of the optimized design features have achieved a power output of 1.2 W (4 W/mm) with 43% power-added efficiency at 10 GHz