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文章基于5G网络中URLLC业务所具备的低时延高可靠特性以及所带来的新的挑战,对空口时延的概念以及URLLC标准进展展开分析,并从减少传输时延间隔、优化资源调度方案等方面对5G无线超低时延技术方案和技术部署展开分析探讨,结果表明,为有效解决时延问题,3GPPR15标准中已经从优化资源调度和缩短传输时间间隔等方面提出可行思路,可为5G网络部署初期低时延业务提供技术支持。 相似文献
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工业自动控制等5G垂直行业对网络传输时延与可靠性有着苛刻的要求。聚焦自动导引车(automated guided vehicle,AGV)协同搬运业务场景,深入分析AGV业务关键质量指标(key quality indicator,KQI)与网络时延可靠性需求。现有的5G低时延技术,比如预调度机制通过大量预留空口时频资源降低传输调度等待时延,降低了频谱效率。此外,无线信道弱覆盖、干扰等质差因素会引发较大的时延抖动,难以满足业务时延可靠性需求。针对现有5G网络面临的挑战,设计了一种端边协同时延确定性保障技术方案,基于业务特征进行网络资源预留,同时感知空口信道状态,开启质差保障机制,提升传输可靠性。测试结果表明,端边协同技术方案可以有效提升时延可靠性,降低大时延抖动与优化业务KQI。 相似文献
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该文研究面向电网业务质量保障的5G 高可靠低时延通信(URLLC)的资源调度机制,以高效利用低频段蜂窝通信系统内有限的频谱和功率资源来兼顾电力终端传输速率和调度时延、调度公平性,保障不同电力业务的通信质量(QoS)。首先,基于URLLC的高可靠低时延传输特性,建立电力终端多小区下行传输模型。然后,提出面向系统下行吞吐量最大化的资源分配问题模型并对其进行分步求解,分别提出基于定价机制与非合作博弈的功率分配算法和基于调度时延要求的改进比例公平算法(DPF)动态调度信道资源。仿真结果表明,提出的资源调度方法能在保证一定传输可靠性和公平性的条件下降低电力终端调度时延,满足不同业务等级的QoS需求,与已知算法对比有一定的优越性。 相似文献
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运营商迎来了基于S D H承载的专线类业务对低时延的新需求,着眼于本地传输网L2及以下的优化传输策略,在量化分析各组网模式时延指标的基础上,对接入层级、复用过程、传输路由三个方面的时延损耗进行理论分析和研究,并结合实际测试案例,提出本地传输网低时延组网模型及资源调度建议. 相似文献
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苏林奋 《电信工程技术与标准化》2020,(7)
5G业务场景uRLLC要求端到端时延小于1ms,低时延是5G专线业务最大的特征。网络架构重构为CU-DU-AAU, CU放置位置会影响时延。通过软管道隔离来实现网络切片会造成带宽抢占,丢包重传会增大时延。通过网络结构调整可以降低线路传输时延,通过FlexE的1.5层快速转发可以降低设备转发时延,通过信道硬隔离隔离可以避免业务拥塞。综合以上技术方案可以有效实现5G专线业务低时延的特性。 相似文献
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超可靠低时延通信(Ultra Reliable Low Latency Communications, uRLLC)是5G移动通信技术的重要场景之一。相较于增强移动宽带(Enhanced Mobile Broadband, eMBB),uRLLC业务有严格的时延、可靠性要求,对数据速率的要求相对较低。在5G NR中,uRLLC业务可以使用微时隙结构抢占eMBB资源进行传输,保证uRLLC业务满足时延要求,同时实现与eMBB业务的复用。基于微时隙结构进行业务抢占的方法,研究了在微时隙结构部署uRLLC业务时,eMBB业务和uRLLC业务的传输性能。首先为eMBB业务用户配置传输资源,然后使用微时隙结构将uRLLC业务穿刺到正在运行的eMBB业务中,在uRLLC业务传输完成后的下一个时隙开展eMBB业务重传以保证uRLLC业务的低时延要求。为了进一步降低uRLLC业务的块误码率,在使用微时隙穿刺的同时,通过设置更大的子载波间隔抑制载波间干扰。通过理论分析评估了该场景中eMBB业务和uRLLC业务的块误码率(Block Error Rate, BLER)和吞吐量性能;在时延性能方面,在对用户... 相似文献
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The authors give an explanation of pupillary latency in terms of nonminimum phase lag. Minimum phase lag is that phase associated with a simple linear lag element; nonminimum phase is associated with a true delay element modeled as exp (-ST). Latency can be accurately modeled by a delay element. The authors experimentally demonstrate that pupillary latency increases with reductions in intensity and increases with frequency of the square-wave stimuli. They summarize these characteristics with a model 相似文献
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以厦门HSPA网络为对象,利用多种数据源重点分析了业务建立过程中RRC和RAB建立阶段的时延,定位了影响时延的终端类型、业务类型、组网策略、信令流程设置等因素,并结合DT测试数据评估了现网业务建立总时延及端到端建立时延. 相似文献
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Lalgudi S.N. Swaminathan M. Kretchmer Y. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):914-931
Ensuring the integrity of the power supply in the power distribution networks (PDNs) of a chip is essential for building reliable high-performance chips. To ensure the power integrity, accurate, and memory- and time-efficient simulation approaches for simulating the power-supply noise in the on-chip PDN are essential. In this paper, a finite-difference formulation based on the latency insertion method (LIM) has been employed for simulating the power-supply noise in the on-chip PDN. A new common-mode type equivalent circuit has been proposed. In this equivalent circuit, a capacitance to ideal ground may not be present at all the nodes. Further, the nodes can be capacitively coupled to each other. To avoid inverting a large nonbanded matrix, a small capacitance to ground is added to a node that did not have any capacitance to ground, and a small series inductance is added to any floating capacitor that did not have any series inductance. Approximate closed-form expressions to compute the values of these capacitances to ground and series inductances have been proposed. The accuracy of the LIM-enabled transient simulation and the accuracy of the proposed closed-form expressions have been demonstrated. The memory and time complexity of the simulation for each time step have been shown to be O(Nn) each, where Nn is the number of nodes in the equivalent circuit. Stability condition is derived for the first time for multidimensional inhomogeneous RLC circuit. A upper bound of the time step is derived from the stability condition. Using this bound on the time step, the runtime of the overall transient simulation has been estimated to be approximately proportional to Nn 2-2.5 for Nn in the order of millions. 相似文献
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Thomopoulos E. Moser L.E. Melliar-Smith P.M. 《Networking, IEEE/ACM Transactions on》2001,9(5):669-680
The Totem single-ring protocol provides reliable totally ordered multicasting of messages to processes in process groups over a single local-area network (LAN) using a logical token-passing ring. The protocol provides two levels of message delivery: delivery in agreed order and delivery in safe order. This paper presents the probability density functions (PDFs) for the latency to message delivery for the Totem single-ring protocol for these two levels of service in the presence of both message loss and token loss. These PDFs are calculated by repeated convolutions of the PDFs for the various components of the latency. The analysis shows that the mean latency to safe delivery is greater than the mean latency to agreed delivery and that the tail of the latency distribution for safe delivery is longer. It also shows that a deterministic arrival process for message generation exhibits lower mean latencies and shorter tails of the latency distribution than a Poisson arrival process 相似文献
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针对 5G 标准中对低延时和编码灵活性的要求, 本文提出了一种高并行度的低密度奇偶校验(Low-Density Parity-Check, LDPC)码编码算法并设计了相应的硬件结构。 编码算法对校验位的计算流程进行了改进, 通过将对应 5G 标准中校验矩阵单对角和双对角结构的不同编码步骤并行化提高了运算速度。 在硬件结构上一方面设计了多路并行的运算结构通过同时求解多个编码步骤降低了处理时延, 另一方面灵活的结构设计使其可以有效地支持5G不同场景下对码长和码率的要求, 并通过分组计算校验位实现了对递增冗余的HARQ (IR-HARQ)方案的支持。仿真结果表明,在 200 MHZ 的系统时钟频率下, 本设计的信息吞吐量可达 35Gbps。 相似文献
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Paraskevas Kalivas Vassilis Vassilakis Chris Meletis Kiamal Z. Pekmestzi 《The Journal of VLSI Signal Processing》2005,39(3):313-322
A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.Paraskevas Kalivas received his Diploma and Ph.D. degree in electrical and computer engineering from the National Technical University of Athens, Greece, in 1990 and 2000 respectively.His research interests include computer arithmetic and efficient realization of arithmetic circuits and digital filters.Vassilis Vassilakis received his Diploma in electrical and computer engineering from NationalTechnical University of Athens, Greece, in 1997. He isworking toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include efficient circuit implemenation of DSP algorithms and java processor architectures.Chris Meletis received his Diploma in electrical and computer engineering from National Technical University of Athens in 1997. Currently, he is working toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include multirate filter banks, digital filter design and their efficient realization.Kiamal Z. Pekmestzi received his Diploma in electrical engineering from the National Technical University of Athens, Greece, in 1975. From 1975 to 1981, he was a research fellow in the Electronics Department of the Nuclear Research Center Demokritos. He received his Ph.D. in electrical engineering from the University of Patras, Greece, in 1981.From 1983 to 1985, he was a professor at the Higher School of Electronics in Athens. Since 1985, he has been with the National Technical University of Athens, where he is currently a professor. His research interests include computer arithmetic, VLSI digital filters and VLSI design automation. 相似文献