东芝功率MOSFET导通阻抗降低60%

日本东芝公司（Toshiba）日前宣布，一种被命名为DTMOS的新式功率MOSFET，由于采用最新的超结合技术，DTMOS的导通电阻（RDSon）仅相当于传统的MOSFET的40％左右，可降低功耗。在采用这项技术的系列产品中第一个产品是0TK15A60S，它的市场定位于电视机电源、家用电器、交流电适配器、照明镇流器。     

应用于压电能量获取系统的超低电压整流器

本文提出了一种应用于压电能量获取系统的高效超低电压整流器。这是通过利用衬底和栅极相连的DTMOS管实现动态控制阈值电压实现的。此外,我们使用输入供电来代替输出供电,这样减少了功率损耗,从而增加了能量转换效率。基于中芯国际0.18μm标准CMOS工艺,仿真结果表明当输入电压为0.2V@100Hz,负载为50kΩ,电压转换效率和能量转换效率分别高达90.5%和95.5%。本文的工作频率为10Hz-1kHz。     

栅极电阻对GaN MOSFET瞬态特性的影响研究

为了研究栅极电阻对GaN MOSFET的开关速率和输出特性中出现振荡的影响,首先利用MOSFET的基本公式对其导通和关断时的输出瞬态电流进行了理论推导,然后通过实验平台测试GaN MOSFET的瞬态电流值,且与理论值对比,验证栅极电阻带来的影响。实验结果表明,GaN MOSFET的瞬态电流值实验值与理论值基本吻合,在导通和关断时,GaN MOSFET的输出瞬态电流和输出电流的高频震荡均随栅极电阻的增加而减小。栅极电阻从10 Ω变化到100 Ω时,导通时开关速率上升率占总开关速率上升率的84.7%,关断时开关速率下降率占总开关速率下降率的54.06%。在栅极电阻为10~100 Ω范围内,GaN MOSFET具有较快的开关速度。     

MOSFET开启的瞬态过程与应对方法分析

阐述MOSFET开启时栅极各个阶段的瞬态过程，MOSFET器件开启过程中栅极每个阶段特定波形的形成原因，从原理上分析了在开启时，栅极的上升台阶在实际应用中带来的问题和危害和规避方法。     

基于栅极限流的SiC MOSFET栅电荷测试方案

SiC MOSFET是一种高性能的电力电子器件,其开通/关断过程中积累/释放的栅电荷Q_g对MOSFET的开关速度、功率损耗等参数有重要影响。通常采用在栅极设置恒流源驱动,对时间进行积分的方法来测量Q_g。为了降低驱动复杂度,提高测试结果精度和可视性,基于双脉冲测试平台的感性负载回路,改用耗尽型MOSFET限制栅极电流实现恒流充电,对SiC MOSFET进行测试。同时利用反馈电阻将较小的栅极电流信号转换为较大的电压信号。实验结果表明：在误差允许范围(±5%)内该测试方案能较为准确地测得SiC MOSFET的Q_g,测试结果符合器件规格书曲线。     

凌特6A MOSFET驱动器驱动标准与逻辑电平N沟道MOSFET,可防止振铃

凌特公司(Linear Technology)推出一个6A MOSFET栅极驱动器LTC4441,使DC/DC控制器能够驱动更高功率的 N 沟道 MOSFET 或多个并联MOSFET,从而提高了DC/DC 控制器的输出功率和效率。LTC4441的栅极驱动电压在5V~8V范围内可调,使设计师能够选择标准门限或逻辑电平 MOSFET,而不仅仅局限于用一种类型的 MOSFET或使用两种不同的MOSFET驱动器。LTC4441还提供具有可调前沿消隐的漏极开路输出,以防止检测功率MOSFET源极电流时振铃。LTC4441具有从 5V~25V的宽输入电源电压范围,为电信和工业系统中增加输出功率能力提供了一…     

高压浮动MOSFET栅极驱动技术

本文介绍了高压浮动MOSFET的应用场合、栅极驱动的的几种常用技术及其优缺点，详细论述了采用IR2125芯片的自举工作模式及充电泵模式的高压浮动MOSFET栅极驱动电路。同时论述了高压浮动MOSFET在汽车制动器中的应用。     

栅极电阻及其影响

在设计DC/DC转换器时,在MOSFET的栅极上串联一个电阻Rg或将它接在MOSFET的栅极与驱动电路之间,这是常见的做法。Rg能够衰减栅极上出现的振荡,但降低了转换器的总效率。如今的转换器中,空间十分宝贵,元件变得越来越小,传统     

德州仪器MOSFET驱动器

德州仪器（TI）推出一款针对N通道互补驱动功率MOSFET的4A高速同步驱动器。TI的TPS28225驱动器以4．5V至8．8V电压控制MOSFET栅极，从而实现了高效率和低电磁卜扰（EMl），在7V至8V电压范围内时，器件效率达到最高。TPS28225实现了14ns自适应停滞时间控制、14ns传输延迟时间、2A大电流电源以及4A吸入驱动功能。针对较低栅极驱动器，驱动器的0．4欧姆阻抗可使功率MOSFET的栅极低于闽值电平，以确保高dV／dT相位节点转换时不会出现贯通电流。内部二极管充电的自举电容器使器件能在半桥配置下使用N通道MOSFET。     

具有极低导通电阻的20V N通道功率MOSFET

SiR440DP系列功率MOSFET在20V额定电压时具有低导通电阻及导通电阻与栅极电荷乘积,在4．5V栅极驱动时最大导通电阻为2．0mΩ,在10V栅极驱动时最大导通电阻为1．55mΩ。导通电阻与栅极电荷乘积是DC／DC转换器应用中MOSFET的关键优值（FOM）,在4．5V时为87。SiR440DP将在同步降压转换器以及二级同步整流及OR—ing应用中用作低端MOSFET。其低传导及切换损耗将确保稳压器模块（VRM）、服务器及使用负载点（POL）功率转换的诸多系统实现功效更高且更节省空间的设计。     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.     

High-voltage and high-temperature applications of DTMOS with reverse Schottky barrier on substrate contacts

In this letter, for the first time, application of dynamic threshold voltage MOSFET (DTMOS) with reverse Schottky barrier on substrate contacts (RSBSCs) for high voltage and high temperature is presented. By this RSBSC, DTMOS can be operated at high voltage (>0.7 V), and exhibits excellent performance at high temperature in terms of ideal subthreshold slope, low threshold voltage and high driving current.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

High performance 0.1 μm dynamic threshold MOSFET using indiumchannel implantation

In this letter, we demonstrate a high-performance 0.1 μm dynamic threshold voltage MOSFET (DTMOS) for ultra-low-voltage (i.e., <0.7 V) operations. Devices are realized by using super-steep-retrograde indium-channel profile. The steep indium-implanted-channel DTMOS can achieve a large body-effect-factor and a low V_th simultaneously, which results in an excellent performance for the indium-implanted DTMOS     

1 V fully balanced differential amplifiers: Implementation and experimental results

We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.     

Simulation of a high performance MOSFET with a quantum wirestructure incorporating a periodically bent Si-SiO2 interface

A MOSFET using a serrated quantum wire structure that produces one-dimensional electron confinement shows excellent subthreshold characteristics and enhanced drive capability compared to a conventional MOSFET with a flat Si-SiO₂ interface. We studied the quantum wire structure with its periodically bent Si-SiO₂ interface using simulations. The potential in the convex regions of the silicon is 0.34 V higher than that in the concave ones when the bending angle is 90°, the bending period is 100 nm, substrate doping is 3.0×10 ¹⁷ cm^-3, and a gate voltage is 0.1 V. Because of this increase in potential in the convex regions, electrons are confined in a narrow width of 13 nm in the convex regions. This 1-D electron confinement effect by the bent Si-SiO₂ interface is clearly observed at low gate voltage and is reduced as the gate voltage becomes higher. Due to the confinement effect, drain current in the MOSFET with this quantum wire structure is 270 times higher than that of a MOSFET with a flat Si-SiO₂ interface at a gate voltage of 0.05 V. In addition, the short-channel effect is more effectively suppressed in this MOSFET than in a conventional MOSFET     

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs.