Novel on-chip fully monolithic integration of GaAs devices with completely fabricated Si CMOS circuits

We monolithically integrated polycrystalline GaAs metal-semiconductor-metal (MSM) photoconductive switches with a completely fabricated Si-CMOS amplifier and obtained a properly functional optical receiver, without altering the Si circuit performance. To our knowledge, this is the first time a fully monolithic on-chip integration has been achieved.     

RF MEMS switches and switch circuits

MEMS switches are devices that use mechanical movement to achieve a short circuit or an open circuit in the RF transmission line. RF MEMS switches are the specific micromechanical switches that are designed to operate at RF-to-millimeter-wave frequencies (0.1 to 100 GHz). The forces required for the mechanical movement can be obtained using electrostatic, magnetostatic, piezoelectric, or thermal designs. To date, only electrostatic-type switches have been demonstrated at 0.1-100 GHz with high reliability (100 million to 10 billion cycles) and wafer-scale manufacturing techniques. It is for this reason that this article will concentrate on electrostatic switches     

基于nRF905射频收发模块的设计

本文介绍了单片射频收发器nRF905的芯片结构、工作模式、射频收发流程以及nRF905片内SPI接口的配置,最后给出了一个典型的应用电路图和电路的设计方法。     

Intimate monolithic integration of chip-scale photonic circuits

In this paper, we introduce a robust monolithic integration technique for fabricating photonic integrated circuits comprising optoelectronic devices (e.g., surface-illuminated photodetectors, waveguide quantum-well modulators, etc.) that are made of completely separate epitaxial structures and possibly reside at different locations across the wafer as necessary. Our technique is based on the combination of multiple crystal growth steps, judicious placement of epitaxial etch-stop layers, a carefully designed etch sequence, and self-planarization and passivation steps to compactly integrate optoelectronic devices. This multigrowth integration technique is broadly applicable to most III-V materials and can be exploited to fabricate sophisticated, highly integrated, multifunctional photonic integrated circuits on a single substrate. As a successful demonstration of this technique, we describe integrated photonic switches that consume only a 300 /spl times/300 /spl mu/m footprint and incorporate InGaAs photodetector mesas and InGaAsP/InP quantum-well modulator waveguides separated by 50 /spl mu/m on an InP substrate. These switches perform electrically-reconfigurable optically-controlled wavelength conversion at multi-Gb/s data rates over the entire center telecommunication wavelength band.     

Improving stereotactic surgery using 3-D reconstruction

In brain surgery, placing a microelectrode from the outer brain to the specific target becomes a new medical resource-reduced technology to alleviate Parkinson's disease. During the operation, the brain atlas is an important and auxiliary tool that cannot completely describe the real brain structure of the patient. Thus, a neurosurgeon usually conjectures the surgical target through experience under the condition that no individual brain atlas is available. Hence, the danger of the surgical operation is high and the automation of the whole process is hard to achieve. In this article, we utilize the patient's computed tomography (CT) data, Schaltenbrand-Wahren (SW) brain atlas, and image processing techniques to develop a novel stereotactic surgical planning system, named Brain Deep Tracer. This system can help a neurosurgeon perform minimally invasive brain surgery (e.g., functional stereotaxy) and diagnose brain disease such as Parkinson's. Generally speaking, this system includes versatile functions such as three-dimensional (3-D) reconstruction of the brain atlas, 3-D localization of the patient's brain CT data, registration of the brain atlas and CT data, fusion of the brain atlas and CT data, and surgical trajectory planning. More importantly, this system can correct the distortion due to the tilt of the head frame and make the localization result more accurate than other systems.     

Hybrid integration of VCSEL's to CMOS integrated circuits

Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4×4 and/or 8×8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 Ω were measured, indicating good electrical contact was obtained. Optical power as high as ~10 mW for a VCSEL with a 20-μm aperture and 0.7 mW with a 6-μm aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS     

Designing digital circuits using 3D nanomagnetic logic architectures

The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.

     

Characterization of Crystalline Carbon Nitride Films Deposited on Si and Si3N4/Si Substrate by RF Magnetron Sputtering System with DC Bias

Crystalline carbon nitride films were deposited on Si and Si₃N₄/Si substrate by reactive RF magnetron sputtering system with chamber heating and DC bias. The deposited films showed -C₃N₄, -C₃N₄ and lonsdaleite phase by XRD, XPS and FTIR. The crystalline morphology was found to gave a hexagonal structure, which has theoretical unit cell of carbon nitride observed in SEM photographs. When nitrogen gas ratio is 70%, RF power is 300 W and DC bias is –80 V, the growth rate of carbon nitride film on Si₃N₄ substrate is 2.2 m/hr, which is a relatively high growth rate compared with those in previously reported papers. The deposited films have thermally stable properties in the range of 650_C to 1,400_C.     

Parallel computation of 3-D electromagnetic scattering using finite elements

The finite element method (FEM) with local absorbing boundary conditions has been recently applied to compute electromagnetic scattering from large 3-D geometries. In this paper, we present details pertaining to code implementation and optimization. Various types of sparse matrix storage schemes are discussed and their performance is examined in terms of vectorization and net storage requirements. The system of linear equations is solved using a preconditioned biconjugate gradient (BCG) algorithm and a fairly detailed study of existing point and block preconditioners (diagonal and incomplete LU) is carried out. A modified ILU preconditioning scheme is also introducted which works better than the traditional version for our matrix systems. The parallelization of the iterative sparse solver and the matrix generation/assembly as implemented on the KSR1 multiprocessor is described and the interprocessor communication patterns are analysed in detail. Near-linear speed-up is obtained for both the iterative solver and the matrix generation/assembly phases. Results are presented for a problem having 224,476 unknowns and validated by comparison with measured data.     

Fabrication process of pzt piezoelectric cantilever unimorphs using surface micromachining

Abstract

This paper discusses the fabrication process and challenges for fabrication of piezoelectric cantilever beam microaccelerometers by using surface micromachining techniques. PZT thin films were used as the piezoelectric material to detect the acceleration of the cantilever beam. In this paper, we discuss in detail the process challenges encountered in piezoelectric microaccelerometers. These major challenges include PZT thin film deposition and encapsulation during final micromachining membrane release.     

射频一体化矢量网络分析仪系统锁相技术

系统锁相技术是矢量网络分析仪的关键技术,主要作用是保证YIG调谐振荡器(YTO)输出频率和参考频率严格同步。介绍了系统锁相技术及辅助锁相电路的设计,并阐述了该电路有效缩短扫描时间的方法,以提高整个矢量网络分析仪测试速度。     

MRI data compression using a 3-D discrete wavelet transform

A low-power system that can be used to compress MRI data and for other medical applications is described. The system uses a low power 3-D DWT processor based on a centralized control unit architecture. The simulation results show the efficiency of the wavelet processor. The prototype processor consumes 0.5 W with total delay of 91.65 ns. The processor operates at a maximum frequency of 272 MHz. The prototype processor uses 16-bit adder, 16-bit Booth multiplier, and 1 kB cache with a maximum of 64-bit data bandwidth. Lower power has been achieved by using low-power building blocks and the minimal number of computational units with high throughput.     

Novel integrated photodetector on Si LSI circuits. Opticallycontrolled MOSFET

We have demonstrated a novel integrated photo-detector on Si large-scale integration circuits. This device integrated the light absorption region on the gate of metal-oxide-semiconductor field-effect transistor (MOSFET), and the long wavelength light controls the current of MOSFET. The GaInAs-InP multiple-quantum-well absorption region and SiO₂ of the MOSFET were directly bonded. From the experimental results, we confirmed that the light-controlled current was increased by shortening the gate length of the MOSFET, and that an 1850 A/W responsivity was obtained in a 3.5-μm gate length device using an irradiation of 1.5-μm wavelength light     

Low-loss inductors built on PECVD intrinsic amorphous silicon for RF integrated circuits

The quality factor (Q) of inductors on silicon (Si) is limited by the series resistance of the metal at low frequency and by the substrate resistivity at high frequency. Oxide is generally used to isolate the useful signal of the inductor from the lossy substrate. However, stoichiometric silica (SiO2) is processed at a high temperature, which eliminates the possibility of post-CMOS integration. By contrast, plasma enhanced chemical vapour deposition (PECVD) amorphous Si can be deposited at a low temperature and is easily integrated with most Si-based processes. Intrinsic amorphous hydrogenated silicon (i-a-Si:H) also displays low conductivity. In this work, i-a-Si:H deposited at a low temperature (250?) is used in a novel approach as the isolation material for planar inductors on Si for RF integrated circuits. An improvementof more than 50% in Q is measured when 1.5 μm i-a-Si:H film is deposited on the Si substrate prior to fabrication of the inductor. This result demonstrates the influence of i-a-Si:H film on the RF performance of an inductor. Intrinsic a-Si:H is shown to be a promising material for the isolation of RF devices on low-resistivity Si.     

Characterization of integration algorithms for the timing analysis of mos vlsi circuits

Displacement techniques used for the timing analysis of VLSI circuits are presented under a new perspective. Their numerical properties such as stability, accuracy, consistency and convergence are investigated.     

Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications

Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.     

Single-breath-hold 3-D CINE imaging of the left ventricle using Cartesian sampling

Objectives

Our objectives were to evaluate a single-breath-hold approach for Cartesian 3-D CINE imaging of the left ventricle with a nearly isotropic resolution of \(1.9 \times 1.9 \times 2.5\,{\text {mm}^3}\) and a breath-hold duration of \(\sim \)19 s against a standard stack of 2-D CINE slices acquired in multiple breath-holds. Validation is performed with data sets from ten healthy volunteers.

Materials and methods

A Cartesian sampling pattern based on the spiral phyllotaxis and a compressed sensing reconstruction method are proposed to allow 3-D CINE imaging with high acceleration factors. The fully integrated reconstruction uses multiple graphics processing units to speed up the reconstruction. The 2-D CINE and 3-D CINE are compared based on ventricular function parameters, contrast-to-noise ratio and edge sharpness measurements.

Results

Visual comparisons of corresponding short-axis slices of 2-D and 3-D CINE show an excellent match, while 3-D CINE also allows reformatting to other orientations. Ventricular function parameters do not significantly differ from values based on 2-D CINE imaging. Reconstruction times are below 4 min.

Conclusion

We demonstrate single-breath-hold 3-D CINE imaging in volunteers and three example patient cases, which features fast reconstruction and allows reformatting to arbitrary orientations.

     

Inclination measurement of human movement using a 3-D accelerometer with autocalibration

In the medical field, accelerometers are often used for measuring inclination of body segments and activity of daily living (ADL) because they are small and require little power. A drawback of using accelerometers is the poor quality of inclination estimate for movements with large accelerations. This paper describes the design and performance of a Kalman filter to estimate inclination from the signals of a triaxial accelerometer. This design is based on assumptions concerning the frequency content of the acceleration of the movement that is measured, the knowledge that the magnitude of the gravity is 1 g and taking into account a fluctuating sensor offset. It is shown that for measuring trunk and pelvis inclination during the functional three-dimensional activity of stacking crates, the inclination error that is made is approximately 2/spl deg/ root-mean square. This is nearly twice as accurate as compared to current methods based on low-pass filtering of accelerometer signals.     

Reconstructing 3-D objects from 2-D boundaries

In this article, two fully implemented algorithms for reconstructing 3-D object models based on two or more 2-D boundaries is introduced. Assuming that the 2-D pixel-based boundaries are generated by using boundary detection algorithms in the image preprocessing session (which is beyond the scope of this article), the 3-D reconstruction goes through two stages. First, the linear regression based line-segmentation algorithm is applied to convert each original pixel-based boundary to a best-fit line segment based polygonal boundary. Then, the 3-D surface reconstruction algorithm is used to cover the surface between each pair of neighboring polygonal boundaries. An important feature of our approach is that it allows easy control of the resolution of the reconstructed 3-D models by setting the error-threshold in the line-segmentation algorithm