GaAs dual-gate MESFET's

Performance of GaAs dual-gate MESFET, including high-frequency noise behavior, was analyzed on the basis of Statz's model. Under the design considerations developed from the analysis, fabrication and characterization of a prototype device were carried out. The present analysis was confirmed to reproduce satisfactorily the performance observed. Minimum noise figure and associated gain observed in the device with two 1-µm gates were; 1.2 dB and 16.7 dB at 4 GHz, 2.2 dB and 16.3 dB at 8 GHz, and 3.2 dB and 12.6 dB at 12 GHz, respectively. More than 35-dB gain controllability was also obtained at 8 GHz.     

Quasi-two-dimensional modeling of GaAs MESFET's

A numerical simulation of GaAs MESFET structures is presented. The approach taken in this paper combines an analytical solution with a full simulation. Poisson's equation, the current continuity equation, and an electron-temperature equation are formulated in terms of a geometry factor that defines the shape of the conducting channel in the MESFET. The transport equations are then solved in one dimension and the channel geometry factor is found analytically. This method was found to be considerably faster than full two-dimensional simulations. The model has been compared to full two-dimensional drift-diffusion and energy-momentum results to determine its validity.     

New modeling of GaAs MESFET's

A first theoretical analysis is given based on a new model of GaAs MESFET's which considers the inherent effects of a free-surface depletion layer between source and gate as well as between gate and drain. Change of surface potential according to the input gate voltage causes variable series resistance and variable gate capacitance to be added to the intrinsic FET. The parasitic effects are now quantitatively estimated and an improved guideline for the design and the fabrication process is given. Detailed calculation of the effects of device parameters for recessed gate structure and some comments on the optimization of n⁺-layers in self-aligned structure are included. The effects of the interfacial depletion layer between active layer and substrate is also estimated in terms of drain voltage and the ratio of total deep levels density in the substrate to donor density in the active layer.     

Distributed numerical modeling of dual-gate GaAs MESFETs

A one-dimensional, numerical gradual channel model is used to examine the behavior of dual-gate GaAs metal-semiconductor field-effect transistors (MESFETs). Distributed numerical models for dual-gate devices do not incur any significant changes over equivalent single-gate device models. Such distributed numerical models are very useful for examining the regions of operation of each channel and the internal field distributions, and they are applicable when the close proximity of the two gates couples the parameters of the individual channels and invalidates the modeling of the device as two channels in series. The author first derives simplified conditions for saturation and nonsaturation of each gated channel, using as a basis the series connection of two single-gate devices. This load-line approach has been found to be very useful for analyzing switching as well as RF bias conditions. Then the model and method used in a numerical gradual channel analysis of the dual-gate FET are described. The results of the analysis are presented and discussed     

Distributed modeling of switching transients in GaAs MESFET's

The transient phenomena resulting from the application of a step bias at the gate electrode of a GaAs MESFET have been simulated using a two-dimensional model. Results emphasizing the effects of the displacement current in high-speed devices are presented. The causes of the delay are discussed for devices of different gate lengths, and the effects of the distributed gate capacitance and the related delay in the drain current characteristics are incorporated in an equivalent circuit model. Analytical expressions derived from large-signal analysis are shown to conform with the results of two-dimensional simulation, allowing for an implementation in simulators such as SPICE     

Analytical modeling of the stationary domain in GaAs MESFET's

A theory for stationary domains in GaAs MESFET's is presented. To the lowest order of approximation the theoretical predictions of maximum domain field and domain voltage agree with those for stable, propagating domains in highly doped Gunn diodes. On the basis of model expressions for the field and impurity dependence of the drift velocity and of the diffusion coefficient, analytical expressions are derived for maximum field, voltage, capacitance, and shape of large and small domains. Specific calculations are performed for channel dopings of interest in GaAs MESFET's. The results are of direct interest in the modeling of GaAs MESFET's and integrated Circuits.     

Accurate modeling for drain breakdown current of GaAs MESFET's

Extensive measurements of a drain breakdown current as a function of device bias are reported in this paper. To represent the measured drain breakdown currents accurately, a new modeling function and an equivalent circuit controlled by two voltages are proposed. This model, when integrated into a large-signal analysis program, improves the accuracy of the simulation     

A finite-element program for modeling transient phenomena in GaAs MESFET's

A two-dimensional finite-element program has been developed for analyzing transient and steady-state characteristics of GaAs devices with arbitrary geometric boundary shapes. The program code consists of two separate programs, GRID and FET, which are discussed in some detail. GRID serves to generate a nonuniform mesh, while FET computes a self-consistent solution of Poisson's and the current continuity equations. A GaAs FET with a trapezoidal recessed gate structure has been studied to demonstrate the capabilities of the program to analyze odd shapes. Current-voltage characteristics were computed for the recessed gate and a planar device. The results from both FET structures are compared and analyzed. In particular the effect of the recessed gate on the field distribution in the device is discussed. Large signal transient behaviors of both devices were examined, and it was found that both device structures produce similar results in steady-state and transient conditions.     

Monolithic dual-gate GaAs FET amplifier

This paper presents the design, fabrication, and performance of a broad-band monolithic dual-gate GaAs FET amplifier. The amplifier has a gain of 3.5-5 dB over the 4.5- to 8-GHz band.     

Submicrometer self-aligned dual-gate GaAs FET

Experimental results show that it is possible to fabricate dual-gate GaAs FET's, with Lg1= 0.6 µm and Lg2= 1.3 µm, using conventional photoprocessing equipment, masks, and alignment tolerances. The initial source mesa establishes both the source and drain edges during the ohmic contact metal deposition. These two edges establish the lengths and positions of the two gates in the channel, during the two subsequent evaporations. Initial experimental devices gave reasonably good small-signal microwave performance: 8-dB packaged net gain with less than 6-dB simultaneous noise figure, at 6 GHz.     

Backgating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr²⁺and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backgating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Reliability Study of GaAs MESFET's

Failure modes have been studied phenomenologically on a small-signal GaAs MESFET with a 1mu m aluminum gate. Three major failure modes have been revealed, i.e., gradual degradation due to source and drain contact degradation, catastrophic damage due to surge pulse, and instability or reversible drift of electrical characteristics during operation. To confirm the product quality and to assure the device reliability, a quality assurance program has been designed and incorporated in a production line. A cost-effective lifetime prediction method is presented that utilizes correlations between RF parameters and dc parameters calculated using an equivalent circuit model. Mean time to failure (MTTF) value of over 10/sup 8/ h has been obtained for the GaAs MESFET for an operating channel temperature of 100/spl deg/C.     

Optical Control of GaAs MESFET's

Theoretical and experimental work for the performance of GaAs MESFET's under illumination from light of photon energy greater than the bandgap of the semiconductor is described. A simple model to estimate the effects of light on the dc and RF properties of MESFET'S is presented. Photoconductive and photovoltaic effects in the active channel and substrate are considered to predict the change in the dc equivalent circuit parameters of the FET, and from these the new Y- and S-parameters under illumination are calculated. Comparisons with the measured S-parameter's without and under illumination show very close agreement. Optical techniques can he used to control the gain of an FET amplifier and the frequency of an FET oscillator. Experimental results are presented showing that the gain of amplifiers can be varied up to around 20 dB and that the frequency of oscillators can be varied (tuning) around 10 percent when the optical absorbed power in the active region of the FET is varied by a few microwatts. When the laser beam is amplitude-modulated to a frequency close to the free-running FET oscillation frequency, optical injection locking can occur. An analytical expression to estimate the locking range is presented. This shows a fair agreement with the experiments. Some suggestions to improve the optical locking range are presented.     

Backdating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr/sup 2+/ and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backdating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Degradation mechanism of GaAs MESFET's

The degradation mechanism of X-band low-noise GaAs MESFET's is examined to obtain meaningful information on a common mode of failure. The devices tested have a half-micrometer gate (Au/ Mo) and source and drain ohmic contacts (Au/Ni/Au-Ge). Zero bias drain conductanceg_{D0}is considered as a representative parameter for degradation during aging. The major failure mode is an increase in series resistance of the ohmic contacts. The amount of degradation, decrease ing_{D0}, is proportional to the square root of aging time, and accompanied by an increase in minimum noise figureF_{min}. A degradation model based on the formation of a high-resistance layer between the ohmic metals and GaAs crystal by a diffusion reaction mechanism is proposed, resulting in excellent agreement between calculated and experimental results. Using ion-microspectroscopy analysis (IMA), diffusion of Ni into GaAs crystal is revealed. Mean time to failure (MTTF) is estimated to be 10⁷-10⁸h at channel temperature of 80°C with an increase inF_{min}of 0.5 dB as failure criterion.     

S-parameter model of dual-gate GaAs MESFET

A simple modelling procedure for the dual-gate MESFET is presented. The model is based on a cascoded connection of two single-gate devices, with each device represented in terms of its s-parameters. These s-parameters are obtained from the overall dual-gate MESFET s-parameters, using accurate deembedding techniques.     

Characterization of Linear and Nonlinear Properties of GaAs MESFET's for Broad-Band Control Applications

GaAs MESFET's designed for control applications have improved switching performance compared to FET's designed for low-noise or high-power amplifiers. A broad-band switching cutoff frequency figure of merit close to 500 GHz has been achieved with both epitaxial and ion-implanted devices having n/sup +/ surface layers and/or channel dopings above 2.0 X 10/sup 17/ cm/sup -3/. Power handling nnder CW conditions is limited in the nonconducting state (FET dc biased into pinchoff) by the difference between the gate breakdown voltage and the pinchoff voltage, while conducting-state power handling is limited by the open-channel current-handling capability. For optimum switching frequency figure of merit, individual gate finger widths greater than those used in amplifier devices for the same maximum frequency of operation are necessary. The large (~5 k Omega) resistor in series with the gate has important ramifications in optimizing the power-handling capability for broad-band applications.     

Beyond-punchthrough current in GaAs MESFET's

In a recent letter published in this journal, Patrick et al. reported on a maximum drain voltage for pinchoff Which varied exponentially with gate length in very short-gate GaAs MESFET's. The I-V characteristics given showed that this variation is associated with beyond-punchthrough drain current. Current flowing across a depleted region is an instance of the triode mode of FET operation described by other researchers in 1966. Triode-mode theory can help in the understanding of the behavior of GaAs MESFET's near pinchoff, including the devices of Patrick et al.     

Optimization of low-noise GaAs MESFET's

This paper presents a device design which is an effective way of reconciling the two conflicting requirements for low-noise GaAs MESFET's. Decreasing the effective value of gate length can be achieved, without penalty of increased gate metallization resistance, by the virtue of a proper gate-recess structure. This effect can be explained by the "effective gate length" concept. The pertinent fabrication techniques and the optimal noise-figure expression are given for an optimized structure with illustrated examples.