DSP在通信系统中的应用与发展

数字信号处理器(DSP)是一种具有特殊结构的微处理器,特别适合于数字信号处理运算,它是当今发展最为迅速和前景最为可观的技术之一.自从20世纪80年代第一片DSP芯片诞生至今,其性能得到了极大的提高,应用领域取得了不断的拓展.日前它己经成为通信、计算机、网络、工业控制以及家用电器等电产品不可或缺的基础器件,尤其在通信领域,数字信号处理器以其实时快速地实现各种数字信号处理算法的优点从而得到了广泛的应用.随着超大规模集成电路技术(VLSI)的高速发展,DSP的性价比也在不断提高.本文就DSP在通信系统中的应用现状及发展趋势做一讨论.     

DSP体系结构在提高实时信号处理方面的作用

数字信号处理器(DSP)是经优化后用于处理实时信号的微处理器。对这些实时信号的处理取决于高速计算的能力。与RISC和CISC微处理器相比，DSP有许多为高速数学运算所进行的结构优化。除了快速数学计算外，设计者发现，一个专门设计的DSP组合了其他的结构化特性以“平衡”体系结构。为支持DSP计算能力。存储器带宽、I／O     

当代DSP及其在现代通信应用中面临的挑战

本文首先从数字信号处理算法的运算特点出发,讨论了数字信号处理运算对DSP硬件性能的要求,当代DSP面临的现代通信的挑战,以及在硬件体系结构上所采取的相应措施,并介绍了DSP在通信中的应用及发展趋势。     

DSP:数字时代的核心引擎

DSP的技术特点 清华大学电子工程系应启珩 DSP器件是一种非常适合于进行数字信号处理运算的微处理器,它特别适用于高度密集、重复运算及大数据流量的信号处理中。DSP相对于一般的微处理器在功能上作了扩充和增强。DSP采用了修正的哈佛(Harvard)结     

集处理器,控制器和DSP于一身的TriCore

TriCore独一无二地把微处理器、微控制器和数字信号处理器（DSP）的功能集中于一个CPU中。TriCore的卓越的实时能力是充分利用这一新体系结构的性能的关键。例如，它能用单个TriCore芯片代替由一个微控制器和一个DSP构成的异型多处理器系统，同时又满足系统对实时性的苛刻要求。TriCore的有效的任务问切换机构使得可以从诸如滤波器计算这种DSP任务快速地切换到控制任务的控制操作。这意味着基于TriCore的系统解决方案比双处理器系统有如下一些优点：1．在两个处理器（以及两种处理）之间所需的同步和通信软件减至最低限度，一个Tr…     

DSP技术的最新发展及其应用现状

概述了数字信号处理(DSP)技术的发展过程,分析比较了DSP处理器与通用微处理器(GPP)的异同;介绍了DSP的最新发展和应用现状;对数字信号处理技术的发展前景和趋势作了预测。     

多媒体产品设计新趋势

传统方法采用RI SC微控制器(MCU)和数字信号处理器(DSP)两种芯片提供嵌入式高级媒体功能.但MCU和DSP各自的作用无法互相替代,而只能协同工作.MCU体系结构很适合有效的异步控制流程,而DSP体系结构主要用于同步、恒定速率的数据流(例如,滤波和变换运算).因为这两类功能在当今的媒体处理应用中都是必需的,所以工程师经常要使用独立的MCU芯片和DSP芯片.这种结合虽然为多种多样的多媒体应用提供了一种很好的处理手段,但是增加了多处理器设计、多种开发工具套件以及学习和调试不同体系结构复杂程度.     

DSP技术综述（2003嵌入式世界研讨置展示会的讲话整理）

DSP的发展历史 数字信号处理是信息领域的一个重要方向。数字信号处理器(DSP)是1982年诞生的一个重要的微处理器类型，1982年由美国的德州仪器公司生产了第一枚单片数字信号处理器，到目前，DSP已经应用的很广泛，也有很多著名的厂家，比如TI、ADI和Motorola等，还有专用的DSP厂家，像Philips等等，目前DSP的运算能力跨越     

DSP嵌入式系统中人机接口电路的分析与设计

分析了DSP嵌入式系统中两种典型的人机接口电路结构,然后重点讨论一种新颖的人机接口电路的体系结构,并以两个具体的电路扩展为例分析了DSP和液晶显示器以及DSP和键盘的接口技术及C语言编程方法。     

世界DSP市场灿然可观

市场走势DSP是DigitalSignalProcessor（数字信号处理器）的缩写,属于MPU（微处理器）的一种,它活跃于声音压缩、图像压缩等数字压缩技术领域,能将声音、图像、温度、压力等种种模拟信号高速转变成数字信号。例如,近年发展极为迅速的便携电话中,DSP将话音模拟信号高速数字化,再通过代码压缩而发送,接收端再经由DSP把压缩了的数字信号复元、伸展成模拟信号。DSP技术曾首先用于军事的声纳和雷达、监测和监听设备,以及气象卫星、地震监测器等。80年代开发出通用产品,逐步进入民用产品各领域。目前用于通信的占一半以上,计算…     

Parallelised max-Log-Map model

A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation     

A 32-b RISC/DSP microprocessor with reduced complexity

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design principles for the implementation of DSP functionality. A DSP unit operates in parallel to an arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data throughput, and deterministic program flow absolutely necessary in DSP applications. Besides offering a basis for general purpose and DSP processing, the RISC philosophy offers a higher degree of flexibility for the implementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit provides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented to provide maximum performance for 16-b data types. While creating a unified base for both application areas, we also minimized transistor count and we reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous     

Functionally Fault-tolerant DSP Microprocessor using Sigma–delta Modulated Signals

The occurrence of soft-faults in digital circuits due to single event upsets (SEU) caused by particle hits has been reported in many works, and it has been claimed that, as the transistor dimensions shrink, multiple and simultaneous faults will be a common scenario in future technologies. Many techniques have been proposed to cope with these kinds of faults, most of them based on hardware or software redundancy. In this work, we present a new paradigm, which is based on signal redundancy, that is, the signal to be processed will contain a certain amount of redundancy, in such a way that, even under the occurrence of multiple faults, the final results will sustain a good resolution for some applications. A DSP microprocessor that uses the technique was prototyped, and some results are presented and compared to typical n-bits binary coded DSP microprocessor architecture, showing the advantages of using the proposed approach.     

Development of a New Robot Controller Architecture with FPGA-Based IC Design for Improved High-Speed Performance

In this paper, a new robot controller architecture is proposed to implement various complex control algorithms for improved high-speed performance. The main thrust of the research is to remove the servo control loop from the digital signal processor (DSP) and implement the high-speed servo loop in a field programmable gate array (FPGA). The main objective of this architecture is to utilize the ultra-high-speed hardwired logic of the FPGA to enhance the overall computational capability and relieve the computational load of the DSP for other tasks. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to calculate model-related control gains/parameters, and it is implemented in the DSP. In tandem, with the newly developed control hardware architecture, an FPGA-based motion control integrated circuit (IC) is designed. Experiments are conducted on an industrial robot manipulator to compare the closed-loop performance with this new control architecture and the traditional one, when the same control algorithm is used. The experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance indeed, especially in high-speed motions.     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

Overview of digital signal processing algorithms, part II - Part 10 in a series of tutorials in instrumentation and measurement

Digital signal processing (DSP) is the process of taking a signal and performing an algorithm on it to analyze, modify, or better identify that signal. To take advantage of DSP advances, one must have at least a basic understanding of DSP theory along with an understanding of the hardware architecture designed to support these new advances. There are several programming techniques that maximize the efficiency of the DSP hardware, as well as a few fundamental concepts used to implement DSP software. This tutorial will touch on the fundamental concepts of DSP theory and algorithms and also provide an overview of the implementation and optimization of DSP software.     

嵌入式Flash CISC/DSP微处理器的研究与实现

本文研究一种新的既具有微控制器功能,又有增强DSP功能的高性能微处理器的实现架构.在统一的增强CISC指令集下,我们将基于哈佛和寄存器-寄存器结构的微处理器模块和单周期乘法/累加器、桶形移位寄存器、无开销循环及跳转硬件支持模块、硬件地址产生器等DSP功能模块以及嵌入式Flash Memory和指令队列缓冲器有机的集成起来,在统一架构下通过单核实现CISC/DSP微处理器,有效地提高了处理器的性能.该微处理器采用0.35μm CMOS工艺实现,芯片面积为25mm².在80M工作频率下,动态功耗为425mW,峰值数据处理能力可达80MIPS.该处理器核可满足片上系统(SOC)对高性能处理器的需求.     

一种高效雷达信号模拟器

为了给某些雷达信号处理算法的研究提供一种有效验证手段,设计此款雷达信号模拟器。系统基于DSP＋FPGA＋DDS架构：以DSP为核心,将AD9957作为基本目标信号产生器,在DSP的控制下FPGA产生基带数据提供给上变频芯片AD9957,完成中频模拟信号的产生。该模拟器创新地利用基于乘法器的迭代算法模拟多种类型雷达回波信号,特别适合产生大时宽信号。这种架构在产生多目标,和差信号方面比传统方法更节省硬件资源。结果表明,该系统集成度高,可扩展性强,数据产生方法高效。     

一种基于FPGA+DSP的处理机硬件架构

为了解决在实时处理中多数合成孔径雷达(SAR)算法存在的运算量大、耗时长等问题,提出基于多核数字信号处理器(DSP)以及串行高速互联接口(SRIO)的一种新硬件解决方法。主要讨论了现场可编程门阵列(FPGA)+DSP架构下采用多核DSP和SRIO实现SAR算法的主要流程,并在多核DSP中使用流水线技术优化快速傅里叶变换(FFT)算法。通过使用多核DSP和流水线技术以及SRIO技术,使数据运算、传输速率更快,达到缩短运算时间的目的。     

Design and Synthesis of a Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras

MPSoC (Multi-Processor System-on-Chip) architecture is becoming increasingly used because it can provide designers much more opportunities to meet specific performance and power goals. In this paper, we propose an MPSoC architecture for implementing real-time signal processing in gamma camera. Based on a fully analysis of the characteristics of the application, we design several algorithms to optimize the systems in terms of processing speed, power consumption, and area costs etc. Two types of DSP core have been designed for the integral algorithm and the coordinate algorithm, the key parts of signal processing in a gamma camera. An interconnection synthesis algorithm is proposed to reduce the area cost of the Network-on-Chip. We implement our MPSoC architecture on FPGA, and synthesize DSP cores and Network-on-Chip using Synopsys Design Compiler with a UMC 0.18  \upmum\upmu\textrm m standard cell library. The results show that our technique can effectively accelerate the processing and satisfy the requirements of real-time signal processing for 256 × 256 image construction.