Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

A 200-MHz sub-mA RF front end for wireless hearing aid applications

A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-μm BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g_m of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz     

Logarithmic analogue-digital converter based on a non-linear analogue-to-digital converter

The paper describes a non-linear analogue-to-digital converter (NL-ADC) whose output is proportional to the natural logarithm of the input voltage. It is based on Maclaurin's series of the natural logarithm function. The design is based on voltage-to-frequency conversion (VFC) and a decimal rate multiplier (DRM). The NL-ADC introduces four digital numbers proportional to the first, second, third and fourth powers of the input DC signal. These numbers are digitally added and subtracted according to the first four terms of Maclaurin's series. A microprocessor-controlled hybrid computer with efficient analogue devices is used in the circuit design and implementation.     

Soft recovery PWM converter with energy recovery and foldingsnubber network suitable for high-power applications

A new soft recovery converter that operates in a more reliable and efficient manner than conventional converters by employing a multiple order folding snubber network (MFSN) and energy recovery network (ERN) is proposed. The new converter is suitable for low-cost, high-voltage and high-power applications operating at output powers of up to several kilowatts     

用自校正方法设计的对数I/V转换器

提出了一种光电流对数压缩I/V转换器设计。该电路能将蓝硅SPD输出的0．1～100μA范围光电流转换成0-3V的模拟电压输出，方便地实现了与MCU的连接。电路核心是制作在同一硅片上两个性能对称的对数放大器，其中之一是自校正参考电路，它的状态由带隙基准源设定。通过对称电路输出的除法运算就消除了温度影响，进而大大提高了温度稳定性，使温度在-20-50℃时，光电流从0．1～100μA的转换误差达1％。     

Reverberation canceling wireless aid for hearing impaired

The stringent requirements on size and power consumption constrain the conventional hearing aid devices. Besides providing an economic and user friendly aid, reverberation/echo cancellation is an important requirement. With the technological advancements, wireless hearing aids exploiting the usage of multi-microphones, mixed signals and RF signals processing circuits, digital signal processing units sound promising to overcome existing constraints. A new wireless hearing aid system is proposed in this paper. Unlike the previously reported wireless hearing aid concept, it needs only one way data transfer from body unit to the earpiece. It helps in minimizing power consumption in the earpiece RF-linked with a body unit with DSP based reverberation canceling scheme. For this purpose, a noise cancellation algorithm is developed based on beam-forming technique. The functioning of the whole system comprising an earpiece and a body unit has been ensured using the Advanced Design System^TM. The ADS compatible behavioral models were developed in order to enable the system level simulation. A comprehensive noise analysis is carried out and validated.     

Digitally-implemented naturally sampled PWM suitable for multilevel converter control

For dynamic closed loop control of a multilevel converter with a low pulse number (ratio of switching frequency to synthesized fundamental), natural sampled pulse-width modulation (PWM) is the best form of modulation. Natural sampling does not introduce distortion or a delayed response to the modulating signal. However previous natural sampled PWM implementations have generally been analog. For a modular multilevel converter, a digital implementation has advantages of accuracy and flexibility. Re-sampled uniform PWM is a novel digital modulation technique which approaches the performance of natural PWM. Both hardware and software implementations for a five level multilevel converter phase are presented, demonstrating the improvement over uniform PWM.     

选择用于电机控制应用的模数转换器

设计师必须解决电流电压监控、光编码器反馈和旋转变压器——数字转换等难题     

Wavelet-based nonlinear AGC method for hearing aid loudnesscompensation

Hearing impairment can often be corrected by medical or surgical treatment, provided the loss is not due to cochlear pathology (sensorineural loss). For sensorineural loss, the only corrective action is to wear a hearing aid. Many perceptual differences between normal and sensorineural hearing-impaired listeners are due to differences in the dB levels at which sound is detected by the ear (auditory threshold) and the associated dynamic range over which it is comfortable to listen to (loudness sensation). To adequately compensate for this, the processing of the auditory signal should be nonlinear and time-varying. Two wavelet-based compression algorithms have been developed: automatic gain control (AGC) with linear amplification and nonlinear compression AGC. The nonlinear AGC is a compression algorithm, which models loudness sensation. The wavelet transform separates the input into seven frequency bands corresponding to the critical bands of the human auditory system. For each frequency band, multiplying the wavelet coefficients by the gain can amplify or compress nonlinearly and smoothly, depending on the signal level, time and spectrum. Results suggest that the nonlinear approach, while maintaining the general spectral structure of the signal, is perceptually superior to linear AGC and compensates better for audibility loss     

A resonant converter suitable for 650 V DC bus operation

A high-frequency resonant power converter configuration suitable for operation on a 650 V (nominal value) DC bus is described. Selection of the high-frequency switch and an appropriate resonant configuration are discussed. It is shown that a series-parallel resonant converter using insulated gate bipolar transistor (IGBT) gated bipolar/MOSFET cascode switches and operating above resonance is suitable for this application. A simplified analysis, a simple design procedure, and detailed experimental results are presented     

A series resonant converter for arc-striking applications

Initiation of a plasma conduction state requires a relatively large voltage to ionize the gas. A new version of the series resonant converter is proposed that uses the magnetizing inductance of the transformer for resonance. This converter is not suitable for most power supply applications, but the unique load characteristics associated with plasma loads make this type of converter well suited for arc striking, while allowing safe operation during the plasma state. A feature of the resonant converter is that the controller need not be complex, thus making it suitable for application in competitive industrial systems. Possible transformer configurations are investigated, which include an air core and a number of ferrite cored transformers. The series resonant converter with the best-suited transformer is verified experimentally in a tungsten inert gas welding application     

Analog circuits for a single-chip infrared controlled hearing aid

All analog circuits for a remotely controllable subminiature hearing aid are presented. It is feasible to integrate all circuits together with an I²L decoder on a single bipolar chip. The volume level and the cutoff frequency of a high-pass filter can be controlled. Besides, the device can be remotely switched at microphone and telephone coil, and switched into a standby mode. All circuits presented have been tested with a semicustom realization.     

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented.DSP modules can be inserted into FPGA conveniently with the proposed architecture,which is much faster when used in the field of digital signal processing compared with traditional FPGAs.An advanced 2-level MUX(multiplexer) is also proposed.With the added SLEEP MODE PASS to traditional 2-level MUX,static leakage is reduced.Furthermore, buffers are inserted at early returns of long lines.With this kind of buffer,the delay of the long line is improved by 9.8%while the area increases by 4.37%.The layout of this architecture has been taped out in standard 0.13μm CMOS technology successfully.The die size is 6.3×4.5 mm~2 with the QFP208 package.Test results show that performances of presented classical DSP cases are improved by 28.6%-302%compared with traditional FPGAs.     

一种新型的适用于数字信号处理的FPGA架构研究

本文提出了一种适用于数字信号处理的FPGA结构,该结构能容易的嵌入DSP模块使得在应用于数字信号处理时FPGA的性能得以改善。除了整体结构,本文提出了一种改进的2级多路选择器。 通过在传统2级多路选择器添加SLEEP MODE路径,降低了其静态功耗。此外,本文在长线中途驱动处添加了缓冲器, 使得长线的延迟降低了9.8%,而面积只增加了4.7%。该结构已经成功流片,采用的是标准的0.13um工艺,裸片面积为6.3 × 4.5mm2,采用QFP208封装。与传统FPGA相比,常用DSP模块测试例子的性能提高了28.6% ~ 302%     

PTAT direct current converter for bias circuit applications

A novel proportional to absolute temperature (PTAT) current converter is presented. Output current gain ratios in excess of 50 are possible without the use of an operational amplifier. Simulation measurements show an output temperature coefficient within 15 ppm//spl deg/C of the reference current over the temperature range of -40 to +85/spl deg/C.     

A rail-to-rail differential quasi-digital converter for low-power applications

This paper presents an ultra low power differential voltage-to-frequency converter (dVFC) suitable to be used as a part of a multisensory interface in portable applications. The proposed dVFC has been designed in 1.2-V 0.18-μm CMOS technology, and it works properly over the whole differential input range (0.6 ± 0.6 V) providing an output frequency range of 0.0–0.9 MHz. The system has been tested for temperature variations from ?40 to +120 °C and supply voltage variations of up to 30 %, being the maximum linearity error in the worse case of 0.017 %. Simulations against common mode voltage variations show a deviation in the output frequency of 0.4 %. This dVFC has power consumption below 60 μW, and it includes an enable terminal that sets the system in a sleep mode (180 nW) while no conversion is request. The dVFC occupies an active area of 250 μm × 150 μm.     

Zero-voltage-switched multiresonant converter for high-power,pulse-load applications

A full-bridge zero-voltage-switched (ZVS) multiresonant converter (MRC) was built for a pulse load with a peak power of 1.44 kW and an average power of 360 W. The converter works with an input-voltage range from 220 to 350 V, and delivers 32 V to the pulse load with a constant peak current of 45 A. The efficiency range of the converter was measured from 82.5 to 90.5%. The maximum efficiency occurs at low line and decreases as the input voltage increases. Detailed analysis and design of the converter, along with experimental results, are presented