Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm² middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

H2/O2 plasma on polysilicon thin-filmtransistor

It is reported for that H₂ plasma followed by O₂ plasma is more effective for passivating grain boundary states in polysilicon thin film. Polysilicon thin-film transistors (TFTs) made after H₂/O₂ plasma treatment can exhibit a turn-on threshold voltage of -0.1 V, a subthreshold swing of 0.154 V/decade, an ON/OFF current ratio I_on/I_off over 1×10⁸, and an electron mobility of 40.2 cm² /V-s     

Enhancement-Mode Buried-Channel $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As/In}_{0.52}hbox{Al}_{0.48}hbox{As}$ MOSFETs With High- $kappa$ Gate Dielectrics

The operation of long- and short-channel enhancement-mode In_0.7Ga_0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have V_t= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm²/Vldrs. For a gate length of 260 nm, the short-channel devices have V_t=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Enhancement-Mode GaAs MOSFETs With an In0.3 Ga0.7As Channel, a Mobility of Over 5000 cm2/V ·s, and Transconductance of Over 475 μS/μm

We present metal-gate high-k-dielectric enhancement-mode (e-mode) III-V MOSFETs with the highest reported effective mobility and transconductance to date. The devices employ a GaGdO high-k (k = 20) gate stack, a Pt gate, and a delta-doped InGaAs/AlGaAs/GaAs hetero-structure. Typical 1-mum gate length device figures of merit are given as follows: saturation drive current, I_d,sat = 407 muA/mum; threshold voltage, V_t = +0.26 V; maximum extrinsic transconductance, g_m = 477 muS/mum (the highest reported to date for a III-V MOSFET); gate leakage current, I_g = 30 pA; subthreshold swing, S = 102 mV/dec; on resistance, R_on = 1920 Omega-mum; I_on/I_off ratio = 6.3 x 10⁴; and output conductance, g_d = 11 mS/mm. A peak electron mobility of 5230 cm²/V. s was extracted from low-drain-bias measurements of 20 mum long-channel devices, which, to the authors' best knowledge, is the highest mobility extracted from any e-mode MOSFET. These transport and device data are highly encouraging for future high-performance n-channel complementary metal-oxide-semiconductor solutions based on III-V MOSFETs.     

ZnO transparent thin-film transistors with HfO/sub 2//Ta/sub 2/O/sub 5/ stacking gate dielectrics

The performance improvement of ZnO thin-film transistors (TFTs) using HfO₂/Ta₂O₅ stacked gate dielectrics was demonstrated. The ZnO TFTs exhibited transistor behaviour over the range 0-10 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm² V^-1 s^-1, 0.5 V/decade and ~10⁶, respectively.     

Logic Suitability of 50-nm In0.7 Ga0.3As HEMTs for Beyond-CMOS Applications

We have experimentally studied the suitability of nanometer-scale In_0.7Ga_0.3As high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm gate-length In_0.7Ga_0.3As HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height (Phi_B) and insulator thickness (t_ins) on the logic characteristics of In_0.7Ga_0.3As HEMTs. The best 50-nm HEMTs with the highest Phi_B and the smallest t_ins exhibit an I_ON/I_OFF ratio in excess of 10⁴ and a subthreshold slope (S) below 86 mV/dec. These nonoptimized 50-nm In_0.7Ga_0.3As HEMTs also show a logic gate delay (CV/I) of around 1 ps at a supply voltage of 0.5 V, while maintaining an I_ON/I_OFF ratio above 10⁴, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Preparation of thin-film transistors with chemical bath depositedCdSe and CdS thin films

The authors have fabricated the thin-film transistor (TFT) with CdSe and CdS semiconductor thin films, prepared by a low temperature chemical bath deposition (CBD) method, as an active layer. The ON-current values of the CdSe-TFTs and CdS-TFTs at a gate bias of 10 V and a source-drain voltage of 10 V are about 100 μA and 5 μA, respectively. The OFF-current values of the CdSe-TFTs and CdS-TFTs at the source-drain voltage of 10 V are less than 10 pA. The fabricated CdSe-TFTs exhibited a field effect mobility of 15 cm²/V-s, threshold voltage of 3.5 V, subthreshold slope of 0.5 V/dec., and ON/OFF current ratios exceed 10⁷. A field effect mobility of I cm ²/V-s, a threshold voltage of 2.6 V, a subthreshold slope of 0.6 V/dec., and an ON/OFF current ratios exceed 10⁶ were observed for CdS TFTs     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

KrF excimer laser annealed TFT with very high field-effect mobilityof 329 cm2/V-s

A thin-film transistor (TFT) with a maximum field-effect mobility of 320 cm²/V-s, an on/off current ratio of 7.6×10⁷ , a threshold voltage of 6.7 V and a subthreshold slope of 0.37 V/decade was fabricated by using pulse laser annealing processes. Amorphous silicon films (a-Si:H) with a very low impurity concentration of 4×10¹⁸ cm^-3 for oxygen, 1.5×10¹⁸ cm^-3 for carbon, and 2×10¹⁷ cm^-3 for nitrogen were deposited by a plasma chemical vapor deposition (CVD) method and annealed by KrF excimer laser (wavelength of 248 nm). The Raman spectroscopy technique was a useful tool for optimizing laser annealing conditions. Experimental results show that two factors are very important for fabricating very-high mobility TFTs: (1) utilizing high-purity as-deposited a-Si:H film; and (2) performing whole laser annealing processes sequentially in a vacuum container and optimizing illumination conditions     

Emission cross sections and spectroscopy of Ho3+ laserchannels in KGd(WO4)2 single crystal

The spectroscopic properties of Ho³⁺ laser channels in KGd(WO₄)₂ crystals have been investigated using optical absorption, photoluminescence, and lifetime measurements. The radiative lifetimes of Ho³⁺ have been calculated through a Judd-Ofelt (JO) formalism using 300-K optical absorption results. The JO parameters obtained were Ω₂=15.35×10^-20 cm², Ω ₄=3.79×10^-20 cm², Ω₆ =1.69×10^-20 cm². The 7-300-K lifetimes obtained in diluted (8·10¹⁸ cm^-3) KGW:0.1% Ho samples are: τ(⁵F₃)≈0.9 μs, τ( ⁵S₂)=19-3.6 μs, and τ(⁵F₅ )≈1.1 μs. For Ho concentrations below 1.5×10²⁰ cm^-3, multiphonon emission is the main source of non radiative losses, and the temperature independent multiphonon probability in KGW is found to follow the energy gap law τ_ph ^-1(0)=βexp(-αΔE), where β=1.4×10^-7 s^-1, and α=1.4×10³ cm. Above this holmium concentration, energy transfer between Ho impurities also contributes to the losses. The spectral distributions of the Ho³⁺ emission cross section σ_EM for several laser channels are calculated in σ- and π-polarized configurations. The peak a σ_EM values achieved for transitions to the ⁵I₈ level are ≈2×10^-20 cm² in the σ-polarized configuration, and three main lasing peaks at 2.02, 2.05, and 2.07 μm are envisaged inside the ⁵I₇→⁵I₈ channel     

Bulk and surface properties of amorphous hydrogenated fluorinatedsilicon grown from SiF4 and H2

A detailed study of the growth of amorphous hydrogenated fluorinated silicon (a-Si:H, F) from a DC glow discharge in SiF₄ and H₂ is discussed. The electrical properties of the films can be varied over a very wide range. The bulk properties of the best films that were measured included an Urbach energy E_u =43 meV, a deep-level defect density N_s=1.5×10¹⁵ cm^-3, and a hole drift mobility of 8×10^-3 cm² V^-1 s^-1, which reflects a characteristic valence band energy of 36 meV. It was found that E_u, N _s, and the density of surface states N_ss are related to each other. Under the deposition condition of the films with the best bulk properties, N_ss reaches its highest value of 1×10¹⁴ cm^-2. It is suggested that in growth from SiF₄/H₂, the density of dangling bonds at the growing surface is very sensitive to the deposition conditions     

A proposed single grain-boundary thin-film transistor

A new Si thin-film transistor (TFT) has been proposed where only one grain-boundary exists at the center of channel, and the source and drain are within single grains with good crystallinity. The device fabricated by an excimer-laser crystallization method at the maximum temperature of 500°C, had the on-off current ratio ≅10⁶ , the field-effect mobility ≅330 cm²/Vs and the subthreshold swing ≅1.1 V/dec, respectively, For the device processed at 800°C, they are >10⁶, >450 cm² /Vs and ≅0.51 V/dec, respectively     

Fabrication of planar optical waveguides in LiB3O5 by 2 MeV He+ ion implantation

The fabrication of planar optical waveguides in LiB₃O ₅ is discussed. Using 2-MeV ⁴He⁺ implantation with a dose of 1.5×10¹⁶ ions/cm² at 300 K, the refractive indexes of a 0.2-μm-thick layer 5.1 μm below the crystal surface are reduced to form optical barrier guides. For this ion dose the maximum change from the bulk values of refractive index at a wavelength of 0.488 μm are 1.5%, 5.25%, and 4% for n_x, n_y, and n_z, respectively. The refractive indexes of the guiding region change by less than 0.02% from the bulk values. The dose dependence of the optical barrier height has been measured. A threshold ion dose of about 0.75×10¹⁶ ions/cm² is required to form a refractive index barrier and ion doses higher than about 2.5×10¹⁶ ions/cm². saturate the refractive index decrease. Waveguide propagation losses for annealed single energy implants of dose 1.5×10¹⁶ ions/cm² are dominated by tunneling and are estimated to be ~8.9 dB/cm for the z-cut waveguides used. Multiple energy implants broaden the optical barrier, and losses of <4 dB/cm have been observed