Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented. The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion. The improved Miller OTA has been successfully verified in a standard 0.35-mum CMOS process. Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

Robust and universal constant-gm circuit technique[operational amplifiers]

A robust and universal circuit technique to maintain a constant transconductance, g_m, in rail-to-rail amplifiers based on input stages made up of parallel-connected complementary differential pairs, is presented. The technique is universal, since it is valid regardless of the g_m/I_D characteristic of input devices. Also, the accuracy does not depend on any condition for matching n- to p-channel input transistors, which makes the technique robust. Experimental results obtained from a 0.8 μm CMOS test-chip prototype, are given     

A versatile half-micron complementary BiCMOS technology formicroprocessor-based smart power applications

A modular, high density 0.5 μm Complementary BiCMOS technology with integrated high-voltage Lateral Diffused MOS (LDMOS) and conductivity modulated Lateral Insulated Gate Bipolar Transistor (LIGBT) structures designed for high performance, multi-functional integrated circuit applications is described. The advantages of VLSI processing and 0.5 μm compatible layout rules have been applied to the design and fabrication of the tight-pitch high-voltage devices without sacrificing the performance of 0.5 μm dual-poly (N+/P+) gate CMOS and complementary vertical bipolar transistors. Single chip integration of VLSI microprocessors with high-voltage and/or high-current input and output functions for “Smart Power” applications can be achieved using this technology     

Active series switch for switched-opamp circuits

A series switch to be used in switched-opamp circuits is proposed. The circuit can be implemented in standard CMOS technology and allows rail-to-rail input and output signals to be processed without a voltage multiplier. Using a 0.5 μm CMOS technology, with a 1 V supply, the circuit exhibits a total harmonic distortion better than -60 dB for a differential signal amplitude up to 1.8 Vpp     

A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier

A 0.9-V 0.5-μA, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode nMOS transistors buffer a bulk-driven pMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low-voltage translinear control circuit     

A Stress-Relaxed Negative Voltage-Level Converter

In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mum triple-well standard CMOS technology, using double-gate-oxide-thickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported     

A programmable piecewise linear large-signal CMOS amplifier

A high-speed CMOS piecewise linear approximation circuit is presented that can be programmed for correction of nonlinearity after fabrication. The basic building block generates a linear segment, for which slope and position can be adjusted. Adjustments to adapt to arbitrary functions are done with floating gate devices fabricated in standard CMOS technology. The circuit is a voltage-to-current converter with an input range of the full power-supply voltage swing. In an implementation with 18 linear segments less than 0.15% error over rail-to-rail input range was achieved for a linear transfer function. Examples of strongly nonlinear transfer functions approximated to 0.5% accuracy are shown. The large-signal 3-dB frequency is 10 MHz. The implementations are done solely with 2-μm channel length devices     

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-μm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCI-X compatible applications.     

Low-Voltage CMOS Rail-to-Rail V-I Converters

This paper presents two CMOS low-voltage rail-to-rail voltage-to-current converters (V-I converter) which could be used as basic building blocks to construct low-voltage current-mode analog VLSI circuits. In each of the circuits, an N-type V-I converter cell is connected in parallel with its P-type counterpart to achieve common-mode rail-to-rail operation. A linear differential relationship of the N-type V-I converter, or its P-type complement, is obtained using a new class-AB linearization technique. In the first rail-to-rail V-I converter circuit, a constant transconductance is achieved through the use of two maximum-current selecting circuits and an output subtraction stage. In the second circuit, a constant transconductance value is obtained by manipulating the DC bias currents of N- and P-type V-I converter cells. Both of the circuits can operate from rail to rail with a power supply of 3V, or less depending on the VLSI technology and the DC bias current level.     

A novel current-mode min–max circuit

This paper presents a new CMOS current mode min?Cmax circuit. The proposed circuit has lower number of transistors, can detect minimum and maximum of the input currents at the same time, shows high precision and has a low cell area. It is designed in 0.25???m standard CMOS technology. Layout of the proposed structure is accomplished to extract the parasitic components, where all the simulations are performed with HSPICE level49 (BSIM3v3) parameters obtained from post layout circuit extraction.     

CMOS highly linear fully differential current conveyor

Design of a CMOS robust low-distortion fully differential second-generation current conveyor (CCII) is presented. The proposed circuit is essential to extend the use of the CCII-based circuits to high-performance VLSI applications. The design avoids using current mirror(s) in the signal path in order to minimise the distortion caused by mismatched mirroring transistors. The proposed circuit is implemented in a standard 0.5 /spl mu/m CMOS technology and its different characteristics are measured. Statistical measurement results show that the proposed fully differential CCII exhibits total harmonic distortion (THD) of -78.9 dB associated with less than 0.1 dB variation.     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

CMOS buffer using complementary pair of bulk-driven super source followers

A power-efficient rail-to-rail CMOS analogue voltage buffer is presented. It consists of a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilised to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 mum CMOS technology to operate at a 1.8 V supply voltage. Simulated results are provided to demonstrate the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68 pF load is as low as -46 dB, while the static current consumption remains under 8 muA.     

Rail-to-rail low-power high-slew-rate CMOS analogue buffer

A low-power rail-to-rail CMOS analogue buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting in suitability for applications with large capacitive loads. Simulated results are provided.     

A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals

A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.     

A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC

CMOS analog-to-digital converters (ADC's) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V_GS plus one V_DSsat between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-μm CMOS occupies an area of 2.4×2 mm² and consumes 10 mW each in analog and digital supplies     

Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies

Bulk-driven MOS transistors lead to a compact low-voltage/low-power input stage implementation. This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced to point out some limitations inherent in multiple-pair input stages and carry out performance comparison, based on experimental data obtained in standard 0.35 μm CMOS technology. The performance achieved by the single-pair bulk-driven input stage can be readily extended to a nanoscale process, as lower supply voltages in scaled technologies are expected. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage and show intrinsic advantages of this approach in some amplifier features, such as linearity and common-mode rejection ratio, as compared to the case of the composite solution.