105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Carrier effective mobilities in germanium MOSFET inversion layer investigated by Monte Carlo simulation

This paper presents the Monte Carlo studies of inversion mobility in Ge MOSFETs covering a wide range of bulk-impurity concentrations (10¹⁴ cm⁻³–10¹⁷ cm⁻³), and substrate bias (0–10 V). Carrier mobilities in Ge MOSFETs have obviously increased compared with those in Si MOSFETs. At low effective field, both electron and hole mobilities have increased over 100%; while at high effective field the increase is reduced due to the effect of surface roughness. Similar to Si MOSFETs, the carrier effective mobilities in Ge MOSFETs also have a universal behavior. The universality of both electron and hole mobilities holds up to a bulk-impurity concentration of 10¹⁷ cm⁻³. On substrates with higher bulk-impurity concentrations, the carrier effective mobilities significantly deviate from the universal curves under low effective field because of Coulomb scattering by the bulk impurity.     

Germanium FETs and capacitors with rare earth CeO2/HfO2 gates

Long channel Ge FETs and capacitors with CeO₂/HfO₂/TiN gates were fabricated by photolithography and gate wet etch. Rare earth CeO₂ in direct contact with Ge was used as a passivating layer producing lowest D_it values in the mid 10¹¹ eV⁻¹ cm⁻² range. HfO₂ cap reduces leakage and improves equivalent oxide thickness scaling of the whole gate stack. The p-FETs show exceptionally high I_ON/I_OFF ratio 10⁶, mainly due to low OFF current, and peak channel mobility around 80 cm²/V s. The n-FETs, although functional, show inferior performance producing ON currents an order of magnitude lower compared to p-FETs.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI pFETs and SOI nFETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 °C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L = 160 nm). Excellent low-field mobility values for electrons in Si nFETs and holes in Ge pFETs were achieved (275 and 142 cm²/V/s resp.).     

Si1−xGex bulk single crystals for substrates of electronic devices

Si_1−xGe_x bulk crystals (0.2<x<0.85) with various B doping levels were grown by the traveling liquidus zone (TLZ) method for fabricating substrates of high mobility electronic devices. Large single crystals with a diameter ranging from 30 to 50 mm were achieved. Si_1−xGe_x crystals were characterized by measuring concentration profile along and perpendicular to the growth axis, indicating good compositional homogeneity. High crystalline quality was evaluated by electron backscatter spectroscopy and X-ray diffraction. Measured hole mobility was higher than the previously reported data for the similar dopant concentration and Ge content, suggesting smaller alloy scattering effects and high crystalline nature in the TLZ-grown Si_1−xGe_x bulk crystals.     

Electrodeposition of <Emphasis Type="Italic">p</Emphasis>-Type Sb<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>Te<Subscript><Emphasis Type="Italic">y</Emphasis></Subscript> Thermoelectric Films

Thermoelectric Sb _x Te _y films were potentiostatically electrodeposited in aqueous nitric acid electrolyte solutions containing different concentrations of TeO₂. Stoichiometric Sb _x Te _y films were obtained by applying a voltage of −0.15 V versus saturated calomel electrode (SCE) using a solution consisting of 2.4 mM TeO₂, 0.8 mM Sb₂O₃, 33 mM tartaric acid, and 1 M HNO₃. The nearly stoichiometric Sb₂Te₃ films had a rhombohedral structure, R[`3]m R\bar{3}m , with a preferred orientation along the (015) direction. The films had hole concentration of 5.8 × 10¹⁸/cm³ and exhibited mobility of 54.8 cm²/Vs. A more negative potential resulted in higher Sb content in the deposited Sb _x Te _y films. Furthermore, it was observed that the hole concentration and mobility decreased with increasingly negative deposition potential, and eventually showed insulating properties, possibly due to increased defect formation. The absolute value of the Seebeck coefficient of the as-deposited Sb₂Te₃ thin film at room temperature was 118 μV/K.     

Effects of increased compressive strain on hole effective mass and scattering mechanisms in strained Ge channels

Effects of increased compressive strain on the hole effective mass in the strained Ge channel structures was systematically studied. The effective mass was found to increase very sensitively with the hole density, and hence accurate strain dependence was evaluated by means of extrapolation of experimentally obtained mass values to a certain hole density (2.0 × 10¹² cm^-2). As a result, it was demonstrated that the effective mass monotonically decreased from 0.195 down to 0.150 m₀ with the increase in the compressive strain from 0.8% up to 2.8%, indicating that introduction of the larger strain into the Ge channel can enhance the hole mobility further. We also studied effects of the increased strain on dominant scattering mechanisms through evaluation of Dingle ratios. It was found that with increasing strain in the Ge channel, the interface roughness scattering became more significant in addition to the impurity scattering. We revealed that the roughness at the top Ge/SiGe heterointerface brought by the increased strain is responsible for the scattering and that this roughness scattering can be effectively suppressed by inserting a modulation-doping layer underneath the channel layer.     

Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime

The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence‐band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe‐shell channel p‐type nanowire FET has demonstrated a strong potential for low‐power and high‐speed applications in 10‐nm‐and‐beyond complementary metal‐oxide‐semiconductor (CMOS) technology.     

Fabrication of Thick Germanium-on-Insulator (GeOI) Substrates

Fabrication of germanium-on-insulator (GeOI) substrates with a 160-nm-thick Ge layer is reported. Such thick GeOI substrates were fabricated by thermal intermixing and subsequent condensation of epitaxially grown high-Ge- content SiGe on Si-on-insulator (SOI) substrates. Transmission electron microscopy revealed that the GeOI layer was single crystalline. The high-resolution rocking curve and reciprocal lattice map obtained from X-ray diffraction measurements showed a relaxed GeOI. This was further confirmed by micro-Raman measurements, where the Ge-Ge optical phonon peak shift represented a nearly strain-free Ge layer. Using this methodology, GeOI substrates with Ge layers 120–160 nm thick have been fabricated with thickness variations of less than 4 nm across 200 mm wafers.     

A comparative 1/f noise study of GeOI wafers obtained by the Ge enrichment technique and the Smart Cut technology

This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Germanium-On-Insulator (GeOI) PMOS transistors processed on different wafers. The wafers are obtained by Ge enrichment technique and by Smart Cut™ technology. The slow oxide trap densities of back interface are used as a figure of merit to evaluate the process. The Smart Cut™ process is evaluated by studying GeOI pMOSFETs, and the enrichment process by studying Si_1−xGe_x (x = 25% and 35%) pMOSFETs. The buried oxide is used as a back gate for experimental purposes. The extracted values are of the same order of magnitude for both processes and are close to those of state of art buried oxide SiO₂/Si interfaces, demonstrating that both the Smart Cut™ and enrichment techniques produce equally good quality interfaces.     

Thermoelectric Properties of Ag-doped Mg<Subscript>2</Subscript>Ge Thin Films Prepared by Magnetron Sputtering

Silver doped p-type Mg₂Ge thin films were grown in situ at 773 K using magnetron co-sputtering from individual high-purity Mg and Ge targets. A sacrificial base layer of silver of various thicknesses from 4 nm to 20 nm was initially deposited onto the substrate to supply Ag atoms, which entered the growing Mg₂Ge films by thermal diffusion. The addition of silver during film growth led to increased grain size and surface microroughness. The carrier concentration increased from 1.9 × 10¹⁸ cm⁻³ for undoped films to 8.8 × 10¹⁸ cm⁻³ for the most heavily doped films, but it did not reach saturation. Measurements in the temperature range of T = 200–650 K showed a positive Seebeck coefficient for all the films, with maximum values at temperatures between 400 K and 500 K. The highest Seebeck coefficient of the undoped film was 400 μV K⁻¹, while it was 280 μV K⁻¹ for the most heavily doped film at ∼400 K. The electrical conductivity increased with silver doping by a factor of approximately 10. The temperature effects on power factors for the undoped and lightly doped films were very limited, while the effects for the heavily doped films were substantial. The power factor of the heavily doped films reached a non-optimum value of ∼10⁻⁵ W cm⁻¹ K⁻² at 700 K.     

Variable temperature hall effect on p-Hg1−xCdxTe grown on CdTe and sapphire substrates by liquid phase epitaxy

Variable temperature Hall effect measurements have been made down to 9–10K on p-type Hg_1−xCd_xTe grown by liquid phase epitaxy on both CdTe and sapphire substrates. Carrier freeze-out was usually observed throughout the measured temperature range. For most samples, the hole mobility was well-behaved and exhibited a maximum at ˜ 35K. Values of acceptor ionization energy E_A and donor concentration N_D were estimated from the data, using a model assuming significant compensation, which provided a good fit to the low temperature data. In addition, values of N_D were also estimated from an analysis of the low temperature mobility using the hole effective mass as a parameter to provide reasonable agreement between the N_D values calculated from the Hall coefficient and mobility data. The measured carrier concentration is a result of close compensation between stoichiometric acceptors and donors, with N_D usually in the low-10¹⁷ cm⁻³ range. Average values of E_A for as-grown, undoped x = 0.32 layers on CdTe and sapphire substrates are 7.4 and 6.6 meV, respectively. An activation energy of 0.84 meV was determined for a Cu-doped x = 0.32 layer that was annealed in Hg vapor to reduce the number of Hg vacancies. The average E_A for undoped Hg-annealed x = 0.22 layers on CdTe substrates is 2.35 meV. Layers with x = 0.32 grown on sapphire substrates have average carrier concentrations of 2.92 (σ = 0.54) × 10¹⁶ cm⁻³, compared with 4.64 (θ = 1.26) × 10¹⁶ cm⁻³ for the same composition layers grown on CdTe substrates.     

Influence of passivating interlayer on Ge/HfO2 and Ge/Al2O3 interface band diagrams

The energy band alignment between Ge, HfO₂ and Al₂O₃ was analyzed as influenced by passivating interlayers (ILs) of different composition (GeO₂, Ge₃N₄, Si/SiO_x). From internal photoemission and photoconductivity experiments we found no IL-sensitive dipoles at the Ge/HfO₂ interfaces, the latter being universally characterized by conduction and valence band offsets of 2.1 and 3.0 eV, respectively. However, in the case of HfO₂ growth using H₂O-based atomic layer deposition, the Ge oxide IL appears to have a narrower bandgap, 4.3 eV, than the 5.4–5.9 eV gap of bulk germania. Accordingly, formation of this IL yields significantly reduced barriers for hole and, particularly, electron injection from Ge into the insulator. Changing to a H-free process for HfO₂ and Al₂O₃ deposition suppresses the formation of the narrow-gap Ge oxide.     

Germanium on sapphire substrates for system on a chip

Germanium on sapphire (GeOS) is proposed for system on a chip applications. Sapphire substrates are demonstrated to exhibit lower rf losses and superior crosstalk suppression compared with oxidised silicon handle wafers. Inductors on sapphire also show higher quality factor and better frequency response than those manufactured on an SOI platform. GeOS substrates have been manufactured by wafer bonding. Bond strengths of greater than 2900 mJ m⁻² have been obtained. Thin GeOS has been achieved by He/H₂ ion cut processes. A self-aligned W gate process on Ge has been established with processing temperature limited to 400 °C. P channel MOSTs exhibit low threshold voltage and a carrier mobility of about 400 cm² V⁻¹ s⁻¹.     

Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Investigation of Multicarrier Transport in LPE-Grown Hg<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Cd<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>Te Layers

A detailed study is presented of multicarrier transport properties in liquid-phase epitaxy (LPE)-grown n-type HgCdTe films using advanced mobility spectrum analysis techniques over the temperature range from 95 K to 300 K. Three separate electron species were identified that contribute to the total conduction, and the temperature-dependent characteristics of carrier concentration and mobility were extracted for each individual carrier species. Detailed analysis allows the three observed contributions to be assigned to carriers located in the bulk long-wave infrared (LWIR) absorbing layer, the wider-gap substrate/HgCdTe transition layer, and a surface accumulation layer. The activation energy of the dominant high-mobility LWIR bulk carrier concentration in the high temperature range gives a very good fit to the Hansen and Schmit expression for intrinsic carrier concentration in HgCdTe with a bandgap of 172 meV. The mobility of these bulk electrons follows the classic μ ~ T ^−3/2 dependence for the phonon scattering regime. The much lower sheet densities found for the other two, lower-mobility electron species show activation energies of the order of ~20 meV, and mobilities that are only weakly dependent on temperature and consistent with expected values for the wider-bandgap transition layer and a surface accumulation layer.     

Solution-processed field-effect transistors based on polyfluorene –cesium lead halide nanocrystals composite films with small hysteresis of output and transfer characteristics

We have designed and investigated electrical and optical properties of solution-processed organic field-effect transistors (OFETs) based on conjugated polymer PFO and perovskite –cesium lead halide nanocrystals (CsPbI₃) composite films. It was shown that OFETs based on PFO:CsPbI₃ films exhibit current-voltage (I-V) characteristics of OFETs with dominant hole transport and saturation current behavior at temperatures 200–300 K. It was found that PFO:CsPbI₃ OFETs have a negligible hysteresis of output and transfer characteristics especially at temperatures below 250 K. The values of the hole mobility estimated from I-Vs of PFO:CsPbI₃ OFETs were found to be ∼2.4 10⁻¹ cm²/Vs and ∼1.9 10⁻¹ cm²/Vs in saturation and low fields regimes respectively at 300 K; the hole mobility dropped down to ∼6 10⁻³ cm²/Vs and 2.8 10⁻³ cm²/Vs respectively at 200 K, and then down to 5.5 10⁻⁵ cm²/Vs at 100 K (in low field regime), which is characteristic of hopping conduction. The effect of sensitivity to light and light-emitting effect were found under application of negative source-drain and gate pulse voltages to PFO:CsPbI₃ OFETs at 300 K. The mechanism of charge carrier transport in OFETs based on PFO:CsPbI₃ hybrid films is discussed.     

Thermal Stability and Phase Purity in Polycrystalline Ba<Subscript>8</Subscript>Ga<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript>46−<Emphasis Type="Italic">x</Emphasis></Subscript>

Polycrystalline Ba₈Ga _x Ge_46−x exhibits promising thermoelectric performance with the figure of merit ZT close to that of single crystals. Polycrystalline Ba₈Ga _x Ge_46−x is promising for applications, but reproducibility and thermal stability of thermoelectric properties need to be demonstrated. Polycrystalline samples of Ba_8+dGa _x Ge_46−x -type clathrates (15.0 ≤ x ≤ 16.8 with varied nominal Ga content and d = 0 or 0.2) were prepared by direct reaction of the elements, followed by ball milling and hot pressing. Trace Ge impurity was observed (<1.0 wt.%) depending on the synthesis method. The electrical resistivity was stable in measurements up to 1000 K, regardless of Ge impurity. However, measurements to 1050 K resulted in irreversible increase in carrier concentration while the carrier mobility remained unchanged.     

Study of the Formation Mechanism of Cu/Ge/Pd Ohmic Contact to <Emphasis Type="Italic">n</Emphasis>-Type InGaAs

This study investigates electrical characteristics and the formation mechanism of the Cu/Ge/Pd Ohmic contact to n-type InGaAs. After annealing the contact at 250°C for 20 min, Cu₃Ge and Pd₁₂Ga₅As₂ compounds formed and Ge diffused into the InGaAs layer, achieving a heavily doped InGaAs layer with a low contact resistivity of 1 × 10⁻⁶ Ω cm². Thermal stability tests were performed on the Cu/Ge/Pd Ohmic contact to InGaAs after Ohmic contact formation, showing no obvious degradation after a 72 h reliability test at 250°C. The results indicate excellent electrical characteristics and thermal stability using Cu/Ge/Pd as an Ohmic contact metal to an n-InGaAs layer.