共查询到20条相似文献,搜索用时 867 毫秒
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Parallel processing is the harnessing of multiple processors to work on the same problem. The aim is to speed up the computational process, ideally by the number of processors used. Parallel processing is increasingly emerging as the key to very-high-speed computation. This article is an introductory overview emphasizing the use of parallel computers for computational engineering 相似文献
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National Instruments 《国外电子测量技术》2007,26(6):1-1
Multicore processing is generating considerable buzz with in the PC industry,largely because both Intel and AMD have released initial versions of their own multicore processors.These first multicore processors contain two cores,or computing engines,located in one physical processor-hence the name dual-core processors. 相似文献
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Kezunovic M. Aganagic M. Skendzic V. Domaszewicz J. Bladow J.K. Hamai D.M. McKenna S.M. 《Power Delivery, IEEE Transactions on》1994,9(3):1298-1307
This paper discusses characteristics of a new digital simulator for protection relay testing. The most demanding design requirement is computation of fault transients under the condition of real-time change of power system configuration due to relay operation. This problem is solved using EMTP computational techniques enhanced with novel numerical solutions for dynamic power system configuration change and nonlinear element modeling. An advanced computer architecture is utilized to achieve further optimization of the execution time for the transients computation code. The main advantage of this design is the use of conventional single processor computer architecture in combination with advanced digital signal processors (DSPs). This makes this simulator an off-the-shelf product with all the benefits of commercially available computers priced at a relatively low cost 相似文献
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双口RAM在DSP与单片机数据通信中的应用 总被引:6,自引:0,他引:6
在多处理器的应用系统中,处理器之间的有效通信是系统能否协同工作的关键。多处理器之间的通信方法有很多种,以双口RAM作为共享存储器来实现2个处理器之间的通信具有实时性好、接口电路简单、数据传输量大等优点。文中介绍了双口RAM内部结构与功能,以及用它来实现DSP与单片机之间通信的接口电路与通信流程,此接口电路同样适合其他类型的多处理器间的通信。 相似文献
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This paper presents an application of neural networks to dynamic dispatch. The proposed method uses a neural network with appropriate noises and can give efficient initial neuron conditions which are specific to the problem. Therefore, convergence to a local minimum can be suppressed. The method is implemented on a transputer, that is one of the efficient parallel processors, and the appropriate number of processors is examined. It can develop optimal and feasible generator output trajectories quickly by applying forecasts of system load patterns to practical thermal generating unit systems 相似文献
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《Engineering & Technology》2007,2(1):40-43
Microprocessor makers have come up with a design that combines two or more independent processors on one chip. Most PC programs, however, cannot take advantage of additional processors since they have been written to run on a single processor. Despite this, programs have still been getting more powerful because of improved processors. Organizing software so that blocks of code in one program can be spread across many processors and run at the same time with increased performance may address this issue. This approach, which has been carried over into transactional memory, gives an operating system more freedom to break a program down into blocks that can be more freely distributed across the processing resources available 相似文献
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Z. Kowalczuk M. Domżalski 《International Journal of Adaptive Control and Signal Processing》2012,26(5):384-399
In this paper, the problem of state estimation in an asynchronous distributed multi‐sensor estimation (ADE) system is considered. In such an ADE system, the state of a plant of interest is estimated by a group of local estimators. Each local estimator based, for example, on a Kalman filter, performs fusion of data from its local sensor and other (remote) processors to compute possibly best state estimates. In performing data fusion, however, two important issues need to be addressed, namely, the problem of asynchronism of local processors and the one of unknown correlation between asynchronous data in local processors. Consequently, there are two main contributions proposed in this paper. The first is a method to deal with asynchronous discrete‐time data based on a continuous‐time stochastic plant model. The second contribution is an asynchronous distributed data‐fusion algorithm. Simulated experiments illustrate the effectiveness of the proposed ADE approach. Copyright © 2011 John Wiley & Sons, Ltd. 相似文献
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TROELS E. KOLDING TORBEN LARSEN 《International Journal of Circuit Theory and Applications》1997,25(2):107-114
This paper addresses the determination of high-order Volterra transfer functions of non-linear multiport networks containing multidimensional non-linear elements. A new method is developed for utilizing parallel computing which is very efficient for approximately 10–20 processors. The utilization of each processor may be as high as 80%–95%. The developed program is very flexible as it is ANSI C++ compatible and may run on both single- and multiprocessor computers. Using about eight processors it is possible to analyse rather complicated non-linear circuits up to ninth order in a few hours. © 1997 by John Wiley & Sons, Ltd. 相似文献
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Chien‐Sung Li Shuenn‐Shyang Wang 《International Journal of Circuit Theory and Applications》2018,46(8):1534-1550
The conventional way to design multi‐input‐multi‐output (MIMO) fast Fourier transform (FFT) processors for MIMO‐orthogonal frequency division multiplexing systems is to adopt a parallel architecture which uses as many single‐input‐single‐output FFT processors as the number of transmit/receive antennas. These MIMO FFT processors can provide high throughput, but they perform with low hardware utilization when there are not all input sequences available. In this paper, we propose a high‐speed MIMO FFT processor which can work efficiently with high throughput and full hardware utilization for variable 1 to 4 input sequences. Our MIMO FFT processor is designed by reordering and distributing data sequences to all data paths and is constructed by some novel modules. Being synthesized by using UMC 0.18‐μm process demonstrates that our 64‐point 4 × 4 FFT can achieve high throughput with full hardware utilization and perform correctly up to 62.25 MHz with low power consumption for variable 1 to 4 input sequences. 相似文献
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A major limitation of the boundary element method (BEM) for the solution of electrical potential problems is the long computational time required. However, a large portion of the calculations involved can be viewed as being parallel in nature and can therefore be computed concurrently. This paper makes an effort to increase the efficiency of the BEM process using transputer-based multiprocessor computing techniques. The algorithms developed may equally well be applied to any multiprocessor system. The application selected to demonstrate the technique is the solution of an electrostatic problem governed by a two-dimensional Laplace equation. A parallel algorithm for problem setup and field extraction using BEM is designed and implemented on a transputer array. Special attention is directed to the utilization of the parallel processors to achieve maximum efficiency. The analysis in this work concentrates on the communication strategies for passing data between processors as well as a consideration of the workload attributed to each processor. The parallel algorithms were implemented using 3L Parallel Fortran; however, the choice of topology for the overall BEM implementation was limited by the fact that certain parts of the algorithm could only utilize a pipeline configuration of processors. Comprehensive results for the parallel BEM algorithm are given and they are encouraging, indicating that parallel processing has much to offer when applied to the boundary element method. 相似文献
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提高预处理共轭梯度法计算大型电网潮流时并行性能的方法 总被引:2,自引:0,他引:2
研究了如何提高预处理共轭梯度(preconditioned conjugate gradient,PCG)法计算大网络交流潮流时的并行性能,提出了一种新的并行处理方法——并行节点分配法,即将节点导纳矩阵和节点出力的数据以节点为单位分派给各个处理器,在各个处理器中完成余下的计算处理部分。算例分析表明,在使用PCG法进行大网络交流潮流计算时,并行节点分配法在并行性能上具有一定的优势,进而为PCG法在大网络交流潮流并行计算中的应用提供了可借鉴的经验。 相似文献
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基于Modbus/TCP的火电厂实时数据集成及网络通信控制器研制 总被引:1,自引:1,他引:0
研制了应用于火电厂给煤系统的火电厂实时数据集成及网络通信控制器.使用Modbus/TCP统一标准协议实现数据的实时通信,将异构设备接口通信归一化.控制器采用双处理器并行通信模式及分任务处理结构,双处理器在握手信号控制下,通过8位并行数据线传输数据,随之进行Modbus/TCP数据封装,将TTL电平信号转换成网络信号,通过工业以太网送至上位监控中心.所研制的控制器解决了现场异构设备不同通信规约带来的数据集成和传输问题.该控制器现场运行稳定可靠,满足研制要求. 相似文献
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With the growing size and complexity of power systems, system analysis—such as transients calculation—takes much time. Hence, fast calculation methods are required. Although parallel processing is a hopeful method, there have been difficulties in the parallel solution of linear equations which appear in power-flow calculations by the Newton-Raphson method. This paper aims at the fast calculation of the power-flow problem by means of parallel processing. In order to improve the suitability to the parallel solution of the differential equation in transients calculation, we assume the use of a direct-mapping parallel processing machine to map directly the network of a power system onto a network of processors. Under this assumption, we propose a new parallel-processing-oriented method in which the linear equation is solved by linear iterations between nodes with Aitken acceleration. We simulate the method on three model power systems and compare this Parallel Iterative Method (PIN) with a Parallel Direct Method (PDM) which uses the banded matrix according to the number of operations required. As a result, we can expect that PIM may solve linear equations faster than PDM with m processors, although the PIM might be inferior to the PDM with m × m processors, where m denotes the half-band width of the banded matrix. 相似文献
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This paper describes the locating system of line‐to‐ground faults on a transmission line by wavelet transform. The possibility of the location with the surge generated by a fault has been theoretically proposed. In order to make the method practicable, we realize very fast processors. We design wavelet transform and location chips, and construct a very fast fault location system by processing the measured data in parallel. This system is realized by a computer with three FPGA processor boards on a PCI bus. The processors are controlled by UNIX and the system has the graphic user interface with X window system. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 140(4): 27–37, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10040 相似文献