A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Long-term bias temperature reliability of P+ polysilicongated FET devices

An instability was found to be associated with +BT stress for P ⁺ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N⁺ poly-gated devices (NNMOS and NPMOS). The instability with the P⁺ poly-gated devices, which is a decrease in threshold voltage (V_t) and an increase in interface state density (D_it), was significantly reduced following N₂ annealing at 400°C. It is shown that adequate reliability for P⁺ poly-gated devices can be achieved for VLSI technologies     

Double-drift-region (p+pnn+) avalanche diode oscillators

The advantages of a double-drift-region avalanche diode oscillator are discussed. Conventional structures (p⁺nn⁺or n⁺pp⁺) are essentially single-drift-region devices in that transit-time delay (for IMPATT mode) and zone transit (for TRAPATT mode) occur in a single region of one impurity type. The proposed structure (p⁺pnn⁺) has two drift regions and is essentially two complementary avalanche diode oscillators in series.     

Ultra-thin silicon-dioxide breakdown characteristics of MOS devices with n+and p+polysilicon gates

In this work we investigate the effect of the gate material on the breakdown characteristics of ultra-thin silicon dioxide films at low voltages (<6 V). When MOS capacitors are stressed with a positive gate voltage, the charge to breakdown and time to breakdown at a fixed oxide-voltage drop are significantly smaller in p+ polysilicon-gate capacitors than in n+ polysilicon-gate capacitors. The results are interpreted in terms of a simple model of hole tunneling resulting from hot-hole generation in the anode by hot electrons entering from the silicon dioxide. Extrapolation of high-voltage-breakdown lifetime measurements for relatively thick-oxide devices to low voltages may be complicated by this mechanism.     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

MBE grown n+-i-δ(p+)-i-n+GaAs V-groove barrier transistor

The three-terminal n⁺-i-δ(p⁺)-i-n⁺V-groove barrier transistor (VBT) has been successfully fabricated by molecular beam epitaxy (MBE). The base terminal is connected to the δ(p⁺), the thin p⁺layer, by depositing aluminum on the etched V-groove. The demonstrated device possesses high potential of ultra-high-frequency (f_{r} > 30-GHz), high-power, and low-noise capability due to carriers transporting by thermionic emission and being controlled by the base-emitter bias.     

Stress-induced leakage current in p+ poly MOS capacitorswith poly-Si and poly-Si0.7Ge0.3 gatematerial

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si_0.7 Ge_0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices     

Device simulation of submicrometer gate p+-i-p+ diamond transistors

Two-dimensional device simulation of submicrometer gate diamond p ⁺-i-p⁺ transistors with a SiO₂ gate insulator was investigated using the MEDICI device simulation program. A large modulation of the source-to-drain current was obtained in the accumulation mode. The computed diamond device characteristics were equivalent or better than the simulation results of 6H-SiC MESFET's. It was concluded that the problems in diamond MESFET associated with the deep acceptor levels due to boron doping can be overcome in the p⁺ -i-p⁺ diamond FET's because of the hole injection and the space charge limited current     

Self-aligned silicided (PtSi and CoSi2) ultra-shallow p+/n junctions

Ultra-shallow p+/n junctions (<100 nm) demonstrating excellent I-V characteristics have been fabricated with self-aligned PtSi. Junctions were formed by rapid thermal annealing (RTA) 〈100〉 Si preamorphized with Sn+ and implanted with BF2+. Subsequently, low-temperature RTA in N2of sputter-deposited Pt produced a 55-nm-thick PtSi layer possessing a remarkably smooth surface and interface, and demonstrating excellent resistance to the aqua regia etch solution. The silicided junctions displayed a sheet resistance of 14 Ω/sq with less than -2-nA . cm^-2reverse-bias leakage at -5 V. In a comparative scheme, similar junction characteristics were obtained using a self-aligned 39-nm-thick CoSi2overlayer.     

Forward current—Voltage and switching characteristics of p+-n-n+(epitaxial) diodes

The forward-biased current-voltage and forward-to-reverse biased switching characteristics of p⁺-n-n⁺epitaxial diodes are investigated. The manner in which the n-n⁺junction affects the flow of injected minority carriers in the epitaxial region is characterized by a leakage parameter a. Experimentally, for diodes with epitaxial film widths much less than a diffusion length, a "box" profile accurately describes the injected minority carriers in the n region. The current is found to increase with increased epitaxial width at a fixed bias. A general switching expression for epitaxial diodes is presented and the validity of the expression is shown experimentally. The experimental values of a, determined independently from the current-voltage and switching characteristics, are in good agreement and show that the leakage of the high-low junction is dominated by the recombination of minority carriers in the n-n⁺space-charge region.     

High-speed p+ GaInAs-n InP heterojunction JFET's(HJFET's) grown by MOCVD

The authors report the high-frequency characteristics of a new type of InP-JFET having p⁺ GaInAs as the gate material grown by MOCVD (metalorganic chemical vapor deposition) using tertiarybutylphosphine (TBP) and tertiarybutylarsine (TBA) as the alternative source for phosphine and arsine, respectively. Using selective wet chemical etching, heterojunction JFETs (HJFETs) with gate length of 0.6 μm led to a unity current gain cutoff frequency and power gain cutoff frequency of 14.3 and 37.5 GHz, respectively. The large valence band discontinuity (▵E_v≈0.37 eV) considerably suppresses hole injection into the channel in the HJFET as compared to homojunction InP-JFETs, making the HJFET a preferred device for high-speed logic circuits based on JFET technology     

Comparison of GIDL in p+-poly PMOS andn+-poly PMOS devices

Gate-induced-drain-leakage (GIDL) in LDD p-MOSFETs has been studied. The emphasis of this paper is on the comparison of GIDL in p ⁺-poly PMOS versus n⁺-poly PMOS devices. Measurements show that the GIDL is less severe in p⁺-poly devices. Clarification for modeling GIDL in devices with different drain structures is also provided     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Avalanche multiplication noise characteristics in thin GaAs p+-i-n+ diodes

Avalanche noise measurements have been performed on a range of homojunction GaAs p⁺-i-n⁺ and n⁺-i-p ⁺ diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise     

The negative bias temperature instability in MOS devices: A review

Negative bias temperature instability (NBTI), in which interface traps and positive oxide charge are generated in metal–oxide–silicon (MOS) structures under negative gate bias, in particular at elevated temperature, has come to the forefront of critical reliability phenomena in advanced CMOS technology. The purpose of this review is to bring together much of the latest experimental information and recent developments in theoretical understanding of NBTI. The review includes comprehensive summaries of the basic phenomenology, including time- and frequency-dependent effects (relaxation), and process dependences; theory, including drift–diffusion models and microscopic models for interface states and fixed charge, and the role of nitrogen; and the practical implications for circuit performance and new gate-stack materials. Some open questions are highlighted.     

Modeling boron diffusion in thin-oxide p+ Si gatetechnology

A network defect model suitable for use in process simulation is presented for the diffusion of B in SiO₂ and, in particular, B in the presence of F and H₂. We find that B diffuses via a peroxy linkage defect the concentration in the oxide of which changes under different processing conditions. From random walk theory it is possible then to calculate the resulting diffusion coefficients. These results are compared with measured diffusivities and empirical adjustments are made     

A novel process to form cobalt silicided p+ poly-Sigates by BF2+ implantation into bilayeredCoSi/a-Si films and subsequent anneal

A novel process that implants BF₂⁺ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided p ⁺ poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide     

Various effects of silicidation on shallow p+ junctionsformed by BF2+ implantation into thin poly-Sifilms on Si substrates

Various effects of silicidation on shallow p⁺ n junctions formed by the scheme that implants BF₂⁺ ions into thin poly-Si films on Si substrates are described. A post-Ni silicidation just slightly improves the preformed junctions of the annealed sample. However, as the sample is first deposited with thin Ni films after the implantation and then annealed, the resulting junctions are much better than the preformed ones. Moreover, as the sample is deposited with Ti films, the resultant junctions are just slightly better the preformed ones     

Anomalous reverse short-channel effect in p+ polysilicongated P-channel MOSFET

The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p⁺ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF ₂ doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator