Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET's using low-frequency (8-Hz)C-Vmeasurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time(t) and temperature(T) dependence for threshold-voltage shift (deltaV_{T}) is represented experimentally asdeltaV_{T}infin log (t/t_{0}), wheret_{0}^{-1} infin exp (-1.0 eV/kT). The positive VTshift appears faster for MOSFET's fabricated with dry O2oxides as gate insulator than for those with HCI oxides. It is also shown that the VTshift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.     

Post-irradiation formation of Si-SiO2 interface states in a hydrogen atmosphere at room temperature

Si MOSFETs were irradiated with x-rays and then exposed to various partial pressures of H₂ at either room temperature or 125 °C. The number of interface traps and the net positive oxide trapped charged were measured during the hydrogen exposure using spectroscopic charge pumping techniques. During the hydrogen exposure the gate electrode was held at a positive bias to maintain a field of 0.65 MV/cm across the gate oxide. It was found that during the room temperature hydrogen exposure the number of interface traps increased by a factor of about two. The change in the oxide trapped charge during hydrogen exposure indicated that the decrease in the number of positively charged oxide traps was approximately the same as the increase in the number of interface traps. The time evolution and bias dependence of these changes are explained by a model that we previously proposed. In this model positively charged radiation induced defects in the oxide crack the H₂ to form H⁺. Under positive gate bias the H⁺ then drifts to the Si-SiO₂ interface where it forms an interface state, while at the same time removing positive charge from the oxide.     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

The effect of silicon gate microstructure and gate oxide process onthreshold voltage instabilities in p+-gate p-channel MOSFETswith fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V_TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V_TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO₂/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V_TP shift     

Characteristics of sub-1/4-μm gate surface channel PMOSFET'susing a multilayer gate structure of boron-doped poly-Si on thinnitrogen-doped poly-Si

This paper reports the effects of a new p⁺ gate structure (MBN gate) on the properties of surface channel PMOSFET's with an extremely thin gate oxide. The MBN gate is a multilayer gate structure of boron-doped poly Si on thin nitrogen-doped poly-Si. The thin nitrogen-doped Si layer effectively suppresses boron diffusion, so that the gate poly Si can be doped with boron in high concentration without the fear of boron penetration. Gate depletion effects are well suppressed. Effective hole mobility is improved due to the reduction of the initial interface state density. The hot-hole induced interface state generation is shown to be the dominant clause of degradation in the 1/4-μm level PMOSFET's, and less Gm degradation is found in the MBN-gate PMOSFET's than in conventional p⁺-gate PMOSFET's. Finally, with respect to the reliability of the gate oxide, a conventional p⁺ gate with boron penetration exhibits an increase in short-time defect related breakdown during constant-current FN stressing. Short-time defect-related breakdown is not observed in the MBN gate but a slight decrease in charge to breakdown     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

Control of the performance of polysilicon thin-film transistor byhigh-gate-voltage stress

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high gate voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO₂ interface     

The effect of native oxide on thin gate oxide integrity

We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using HF-vapor treated and H₂ baked processes. Furthermore, an extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm² and a large charge injection of 7.9×10⁴ C/cm². The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole traps     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

A study of interface trap generation by Fowler-Nordheim andsubstrate-hot-carrier stresses for 4-nm thick gate oxides

The generation of interface traps by different stresses to 4-nm thick SiO₂ gate oxide is studied. Four different kinds of constant current stresses were applied. The interface-trap density (D _it) generation due to hot holes under V_G<0 Fowler-Nordheim (FN) stress was characterized using quantum-yield measurement and substrate-hot-hole (SHH) stress. The interface-trap density (D_it) generated by SHH stress increases as gate-oxide field increases. Substrate-hot-electron (SHE) stress generates much less interface-trap density (D_it) than SHH stress. It is also observed that N₂O-grown gate-oxide has smaller hole-injection probability but larger electron-injection probability than O₂-grown oxide. N₂O-grown gate oxide is shown to have less SHH stress-induced interface traps than O₂-grown oxide in p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) devices     

Hot-carrier-induced degradation in reoxidized-nitrided-oxiden-MOSFETs under mixed AC-DC stressing

Reduced degradation rate can be observed for reoxidized-nitrided-oxide (RNO) n-MOSFETs under dynamic stressing versus the corresponding static stressing. A new degradation mechanism is proposed in which trapped holes in gate oxide are neutralized by the hot-electron injection, with no significant generation of interface states because of the hardening on the Si-SiO₂ interface by nitridation/reoxidation steps. The RNO device degradation during AC stressing arises mainly from the charge trapping in the gate oxide rather than the generation of interface states. Moreover, the AC-stressed RNO devices are significantly inferior to the fresh RNO devices in terms of DC stressing, possibly due to lots of neutral electron traps in the gate oxide resulting from the AC stressing     

Analysis of CMOS transistor instabilities

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

Dynamic behavior of the buildup of fixed charge and interface states during hot-carrier injection in encapsulated MOSFET's

The aging behavior of MOSFET's encapsulated with various types of capping layers was studied. Aging consisted of room-temperature pulsed gate bias operation with a drain-to-source voltage sufficient to cause avalanche multiplication in the channel. It was verified by secondary ion mass spectroscopy (SIMS) profiling that plasma silicon nitride capping layers introduce 2-4 times more hydrogen at the Si-gate oxide interface than exists in uncapped devices. Capping materials that serve as hydrogen barriers contribute to device aging by trapping hydrogen that is liberated during hot-carrier emission into the gate oxide. The aging dynamics begin with buildup of negative fixed charge in the gate oxide near the drain, followed by the buildup of positive fixed charge and interface states. The generation of these interface states and the negative fixed charge was found to have a spatial and time dependence. Long anneals at temperatures above 350°C delay the onset of the aging process. A model that accounts for these observations is proposed.     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.     

Analysis of hot-carrier-induced aging from 1/f noise in short-channel MOSFET's

The 1/f noise of short-channel n-type MOSFET's is measured in the weak inversion regime before and after an electrical stress. The noise increase which follows the aging is shown to be due to an electrically induced generation of traps in the gate oxide rather than fast interface states. Noise experiments prove that the degradation occurs in a narrow region (less than 50 nm) near the drain. Created traps also appear to have an inhomogeneous energy profile.