A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

This brief presents a high-throughput dual-field elliptic-curve-cryptography (ECC) processor that features all ECC functions with the programmable field and curve parameters over both the prime and binary fields. The proposed architecture is parallel and scalable. Using 0.13-$muhbox{m}$ CMOS technology, the core size of the processor is 1.44 $hbox{mm}^{2}$ . The measured results show that our ECC processor can perform one 160-bit point scalar multiplication with coordinate conversion over the prime field in 608 $muhbox{s}$ at 121 MHz with only 70.0 mW and the binary field in 372 $muhbox{s}$ at 146 MHz with 82.1 mW. The ECC processor chip outperforms other ECC hardware designs in terms of functionality, scalability, performance, cost effectiveness, and power consumption. In addition, the system analysis shows that our design is very efficient, compared with the software implementation for realistic security applications.      

Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography

We present a design framework that consists of a high-throughput, parallel, and scalable elliptic curve cryptographic (ECC) processor, and its cost-effectiveness methodology for the design exploration. A two-phase scheduling methodology is proposed to optimize the ECC arithmetic over both ${rm GF}(p)$ and ${rm GF}(2^m)$. Based on the methodology, a parallel and scalable ECC architecture is also proposed. Our dual-field ECC architecture supports arbitrary elliptic curves and arbitrary finite fields with different field sizes. The optimization to a variety of applications with different area/throughput requirements can be achieved rapidly and efficiently. Using 0.13-$mu$m CMOS technology, a 160-bit ECC processor core is implemented, which can perform elliptic-curve scalar multiplication in 340 $mu$s over ${rm GF}(p)$ and 155 $mu$s over ${rm GF}(2^m)$, respectively. The comparison of speed and area overhead among different ECC designs justifies the cost-effectiveness of the proposed ECC architecture with its design methodology.      

Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation

State-of-the-art application-specific instruction set processors (ASIPs) allow the designer to define individual prefabrication customizations, thus improving the degree of specialization towards the actual application requirements, e.g., the computational hot spots. However, only a subset of hot spots can be targeted to keep the ASIP within a reasonable size. We propose a modular Special Instruction composition with multiple implementation possibilities per Special Instruction, compile-time embedded instructions to trigger a run-time adaptation of the instruction set, and a run-time system that dynamically selects an appropriate variation of the instruction set, i.e., a situation- dependent beneficial implementation for each Special Instruction. We thereby achieve a better efficiency of resource usage of up to 3.0 $times$ (average 1.4 $times$) compared with current state-of-the-art ASIPs, resulting in a 3.1$times$ (average 1.4$times$ ) improved application performance (compared with a general purpose processor up to 25.7$times$ and average 17.6$times$ ).      

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.      

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 $times$ 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplication. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is performed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise accumulation during ADC readout. A 128 $times$ 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35$ mu{hbox {m}}$ standard CMOS technology. The 4.4 mm $times$ 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain ($K_v$) and charge-pump (CP) current over C ($I_{CP}/C$), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using $K_v$ and $I_{CP}/C$ calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 $~$MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 $~$Mbps (625$~$MHz) the reduction of spectrum peak amplitude is 18.6$~$dB which is 2.3$~$dB better than the reduction obtained without calibration.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

All-Optical Label Swapping of Scalable In-Band Address Labels and 160-Gb/s Data Packets

Scalability and photonic integration of packet switched cross-connect nodes that utilize all-optical signal processing is a crucial issue that eventually determines the future role of photonic signal processing in optical networks. We present a 1 $times$ 4 all-optical packet switch based on label swapping technique that utilizes a scalable and asynchronous label processor and label rewriter. By combining $N$ in-band labels at different wavelengths (within the bandwidth of the payload), up to $2^{N}$ possible addresses can be encoded. The proposed label processor requires only $N$ active devises to process the $2^{N}$ addresses that makes this label processing technique scalable with the number of addresses. Experimental results showed error-free packet switching operation at 160 Gb/s. The label erasing and new label insertion operation introduces only 0.5 dB of power penalty. These results indicate a potential utilization of the presented technique in a multi-hop packet switched network.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Fast Hardware Algorithm for Division in $ hbox{GF}(2^{m})$ Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions

We propose a fast hardware algorithm for division in $hbox{GF}(2^{m})$ based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circuit computes division in $m$ clock cycles, whereas the previously proposed circuits take $2m - 1$ or more clock cycles.      

Higher Radix and Redundancy Factor for Floating Point SRT Division

The execution performances of the Sweeney, Robertson, Tocher (SRT) division algorithm depend on two parameters: the radix- $r$ and the redundancy factor $rho$. In this paper, a study of the effect of these parameters on the division performances is presented. At each iteration, the SRT algorithm performs a multiplication by the quotient digit ${q}_{{i}+1}$ . This last can be just a simple shift, if the digit ${q}_{{i}+1}$ is a power of two $({q}_{{i}+1}=2^{k})$ , otherwise, the SRT iteration needs a multiplier. We propose, in this work, an approach to circumvent this multiplication by decomposing the quotient digit ${q}_{{i}+1}$ into two or three terms multiples of 2. Then, the multiplication is carried out by simple shifts and a carry save addition. The implementation of this approach on Virtex-II field-programmable gate-array (FPGA) circuits gives best performances than the approach which uses the embedded multipliers 18 $times$ 18 bits. The iterations delays are operands sizes independent. The reduction tree delays are at most equivalent to the delay of two Virtex-II slices. This approach was tested for the 4, 8, and 16 radixes in the two cases of minimum and maximum redundancy factors. By this study, we conclude that the use of the radix-8 with a maximum redundancy factor gives the best performances by using our approach for the double precision computation of the SRT division.      

Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

Separated Unicast/Multicast Splitter-and-Delivery Switch and Its Use in Multicasting-Capable Optical Cross-Connect

We propose a novel separated unicast/multicast splitter-and-delivery (SUM-SaD) switch for mixed unicast and multicast traffic. Only multicast connections undergo extra splitting loss but are compensated by incorporated optical amplifiers. A typical multicasting-capable optical cross-connect is constructed by using the proposed SUM-SaDs. Theoretically, we prove that it is strictly nonblocking for both unicast and multicast connections if $d=N/2$, where $N$ and $d$ are the dimension of SUM-SaD and the number of SaD input ports, respectively. Therefore, $d$ means the maximum accommodated trees in the SUM-SaD. To save cost, $d$ can be less than $N/2$ , and the throughput performance is investigated by simulation. The results show that the throughput is improved when $d$ increases. In the experiment, we construct a 4 $times$ 4 SUM-SaD prototype and measure the bit-error rate (BER) of unicast connection, multicast connection with or without optical amplifier. There is no clear BER difference between them for the small dimensional SUM-SaD switch.      

Improved Microwave Noise Performance by SiN Passivation in AlGaN/GaN HEMTs on Si

Effects of silicon nitride (SiN) surface passivation by plasma enhanced chemical vapor deposition (PECVD) on microwave noise characteristics of AlGaN/GaN HEMTs on high-resistivity silicon (HR-Si) substrate have been investigated. About 25% improvement in the minimum noise figure $(NF_{min})$ (0.52 dB, from 2.03 dB to 1.51 dB) and 10% in the associate gain $(G_{rm a})$ (1.0 dB, from 10.3 dB to 11.3 dB) were observed after passivation. The equivalent circuit parameters and noise source parameters (including channel noise coefficient $(P)$, gate noise coefficient $(R)$, and their correlation coefficient $(C)$ ) were extracted. $P$ , $R$ and $C$ all increased after passivation and the increase of C contributes to the decrease of the noise figure. It was found that the improved microwave small signal and noise performance is mainly due to the increase of the intrinsic transconductance $(g_{{rm m}0})$ and the decrease of the extrinsic source resistance $(R_{rm s})$.      

Sensor Selection via Convex Optimization

We consider the problem of choosing a set of $k$ sensor measurements, from a set of $m$ possible or potential sensor measurements, that minimizes the error in estimating some parameters. Solving this problem by evaluating the performance for each of the $m choose k$ possible choices of sensor measurements is not practical unless $m$ and $k$ are small. In this paper, we describe a heuristic, based on convex optimization, for approximately solving this problem. Our heuristic gives a subset selection as well as a bound on the best performance that can be achieved by any selection of $k$ sensor measurements. There is no guarantee that the gap between the performance of the chosen subset and the performance bound is always small; but numerical experiments suggest that the gap is small in many cases. Our heuristic method requires on the order of $m^{3}$ operations; for $m=$ 1000 possible sensors, we can carry out sensor selection in a few seconds on a 2-GHz personal computer.      

Anisotropic Transient and Stationary Electron Velocity in Bulk Wurtzite GaN

The theoretical calculation of transient electron velocity overshoot in wurtzite $c$-axis GaN indicates a higher transient overshoot peak for transport in the basal plane ( $Gammahbox{-}M$ and $Gamma hbox{-}K$) than along the growth direction ($Gammahbox{-}A$ ). Characteristic rise times for the transient overshoot peak are found to be shorter for transport along the $c$-axis. Stationary electron velocity is significantly larger for transport oriented in the basal plane than along the $c$ -axis. No significant anisotropy is observed, however, in either the transient or steady-state electron velocity as a function of field orientation within the basal plane itself. The higher peak transient and stationary velocities in the basal plane are directly attributable to the anisotropy of the electronic dispersion, which exhibits lower effective mass along the $Gammahbox{-}M$ and $Gammahbox{-}K$ directions and greater nonparabolicity along the $Gammahbox{-}A$ direction.