Simple and accurate approaches to implement the complex trans‐conductance suited for time‐domain simulators for small‐signal and large‐signal table‐based models

This paper focuses on the implementation of table‐based models of high‐frequency transistors for time‐domain simulators at microwave and mm‐wave frequencies. In this frequency range, the channel is not capable of responding to the excitation instantaneously therefore, a delay‐time exists between the channel response and the channel excitation. This delay is represented by a complex trans‐conductance in terms of circuit elements. The high‐frequency models of transistors are required to have the implementation of complex trans‐conductance, where the complex part accounts mathematically for the delay‐time between the channel response and the channel excitation. This paper presents simple and accurate approaches to incorporate the complex trans‐conductance in both small‐signal and large‐signal table‐based models for time‐domain simulators (MOS‐AK International Meeting. Eindhoven, Netherlands, April 2008). Implementation approach for each model, small‐signal and large‐signal, is presented in separated sections. In the first step, the delay is realized by the introduction of an ideal transmission line between the channel excitation and the channel response. As transmission lines are not generally suitable for time‐domain simulations, a lumped element equivalent network is introduced in the second step. The latter approach is fully compatible with time‐domain simulators but frequency limitation, determined by the delay‐time value itself, is introduced. Then the implementation of the complex trans‐conductance in large‐signal model is introduced. In terms of large‐signal behavior, delay‐time is important to achieve a non‐quasi static model. Yet again there is limitation in terms of the frequency range that is determined by the delay value itself. The methodology is illustrated on the small‐signal and the large‐signal equivalent circuit of a Multi‐Fin MOSFET transistor. Simulations are carried out by Cadence Spectre and Agilent ADS simulators, and comparisons are carried out between the simulation results and the measurements. Copyright © 2010 John Wiley & Sons, Ltd.     

Interactive compact device modelling using Qucs equation‐defined devices

Recent trends in compact device modelling and circuit simulation suggest a growing movement towards standardization of Verilog‐A as a vehicle for semiconductor device specification and model interchange among commercial and open source simulators. This paper introduces a nonlinear equation‐defined device (EDD) characterized by current, voltage and charge equations with a similar syntax to Verilog‐A. The EDD has been implemented in Qucs and used extensively as a central feature in an interactive modelling system that allows straightforward prototyping of compact device models prior to translation into Verilog‐A. To illustrate the properties and the use of the Qucs EDD a number of examples centred on well‐known SPICE models are described. Copyright © 2008 John Wiley & Sons, Ltd.     

Circuit modeling for ultra‐wideband Tx‐Rx antenna systems based on frequency domain S‐parameters

This paper presents a circuit modeling procedure for Ultra‐wideband (UWB) Tx‐Rx antenna systems based on frequency domain S‐parameters. The modeling used an existing two‐port network's model consisting of four SPICE analog behavioral modules. The accuracy of the model has been validated by comparing its transient response with the measurement result using an oscillograph. This model can be used for the co‐design of the UWB Tx‐Rx antenna system with transmitters and receivers in circuit simulators. In the study, Tx‐Rx antenna systems using planar bow‐tie antenna and horn antenna with ultra‐wide bandwidths are used as examples. Copyright © 2010 John Wiley & Sons, Ltd.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

Why‐ and how‐ to integrate Verilog‐A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog‐A compact models in SPICE‐like simulators. Modifications in the models' Verilog‐A source code may be required prior to their conversion into low‐level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog‐A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.     

On the simulation of fast settling charge pump PLLs up to fourth order

In this paper, we discuss three different models for the simulation of integer‐N charge‐pump phase‐locked loops (PLLs), namely the continuous‐time s‐domain and discrete time z‐domain approximations and the exact semi‐analytical time‐domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time‐domain model are introduced and the results are compared with those obtained by means of the s‐domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB‐OFDM UWB systems. Copyright © 2010 John Wiley & Sons, Ltd.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Analytic transient solution of SCFL logic gates

In this paper we propose the analytical solution of switching transients for SCFL logic gates. The analysis of an SCFL logic gate is carried out without linearization and can be brought back to multiple analyses of a basic cell, given by a differential pair with switching input voltages and a variable tail current, to take the effect of series‐gating into account. The differential equation for this cell is a Riccati equation, if a quadratic current–voltage relationship is used for the transistors, and it can be solved by the infinite power series method, in case of polynomial input signals. An algorithm is proposed to analyse the full transient of a complex SCFL gate. This provides a closed form expression for transient signals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time‐domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AH technology, and a good agreement between the proposed model and SPICE simulations using complex device models is obtained. Copyright © 2005 John Wiley & Sons, Ltd.     

Fast and accurate analysis of one‐dimensional arrays of dynamic PWL cells

This paper describes a new method for the time‐domain analysis of one‐dimensional arrays of dynamic piecewise linear cells. The method exploits the local connectivity, typical of cellular arrays, and the piecewise linear behaviour of the v–i characteristic of the non‐linear elements to obtain a piecewise analytical expression of the solution. Examples demonstrate the accuracy and the efficiency, in terms of CPU‐time, of the proposed method with respect to standard simulation tools as SPICE and the numerical integration of a system of ordinary differential equations. Copyright © 2001 John Wiley & Sons, Ltd.     

An efficient numerical technique for the implementation of SSLS and cyclostationary noise analysis in physics-based device simulators

The paper introduces a novel numerical technique for the efficient implementation of SSLS and cyclostationary noise analysis in physics-based device simulators calculating the time-varying device working point exploiting the harmonic balance technique. The technique is based on a mixed time-frequency evaluation of the matrix-vector products involved in the iterative solution of linear systems, indispensable for the simulation of realistic 2D or 3D device structures, relevant to the previous analyses. The algorithm, applicable to all PDE systems where the memory part is linear, allows for a significant improvement in the computation time with respect to the direct, frequency-domain implementation.     

Finite element power diode model optimized through experiment‐based parameter extraction

This paper presents a finite element physics‐based power diode model with parameters established through an extraction procedure validated experimentally. The model core is a numerical module that solves the ambipolar diffusion equation through a variational formulation followed by an approximate solution with the finite element method. Other zones of the device are modeled with classical methods in an analytical module. This hybrid approach enables accurate modeling and simulation of power bipolar semiconductor devices, using standard SPICE circuit simulators, with low execution times. As physics‐based models need a significant number of parameters, an automatic parameter extraction method has been developed. The procedure, based on an optimization algorithm (simulated annealing), enables an efficient extraction of parameters using some simple device waveform measurements. Implementation details of power diode model, in IsSpice simulator, are presented. Experimental validation is performed. Results prove the usefulness of the proposed methodology for efficient design of power circuits through simulation. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐Noise Fully Differential Amplifiers Using JFET‐CMOS Integration Technology for Smart Sensors

In this paper, CMOS‐based low‐noise amplifiers with JFET‐CMOS technology for high‐resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front‐end circuit in many sensor applications. Low‐noise JFET devices are used as input pair of the input differential stages or source‐grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET‐CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET‐CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise‐reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about − 18 dB at 2.5 Hz. JFET‐CMOS technology is very effective in improving the signal‐to‐noise ratio (SNR) of a sensor interface circuit with CMOS‐based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Analysing the operation of the basic pass transistor structure

Pass transistor logic has become important for the design of low‐power high‐performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters. Copyright © 2006 John Wiley & Sons, Ltd.     

Cross‐correlation‐based trans‐impedance amplifier for current noise measurements

This work proposes a cross‐correlation‐based trans‐impedance amplifier for current noise measurements in the low‐frequency range. The proposed solution is compared with the classical cross‐correlation trans‐impedance amplifier showing a lower background noise. Furthermore, a three‐step measurement method, based on the new trans‐impedance amplifier, is proposed to cancel the residual background noise. SPICE simulations and noise measurements performed on prototype circuits demonstrate the validity of the proposed approach. Copyright © 2008 John Wiley & Sons, Ltd.     

A low distortion CMOS continuous‐time common‐mode feedback circuit

In high‐gain fully differential operational amplifier (FD op‐amp) design, the output common‐mode (CM) voltage of the FD op‐amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common‐mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuous‐time CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded‐cascode op‐amp and the other is the Multiply‐by‐Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog‐to‐digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

A new algorithm for shot noise removal in medical ultrasound images based on alpha‐stable model

Ultrasonic images are generally affected by multiplicative shot noise. Shot noise filtering is thus a critical pre‐processing step in medical ultrasound imagery. This paper analyses and models the coefficients of 2‐D multi‐resolution wavelet decomposition of logarithmically transformed images using alpha‐stable distribution model. Consequently, we propose a new function that performs a non‐linear operation on the data of classifying the coefficients, thus achieving a novel form of noise removal based on multi‐resolution wavelet decomposition and the alpha‐stable model. We compare our new technique with current shot noise reduction methods applied on actual ultrasound medical images and simulations results show that the proposed new method is more robust than the methods based on Gaussian assumption. Copyright © 2006 John Wiley & Sons, Ltd.