Multithreaded processor architectures

The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution. When a long-latency operation occurs in one of the threads, another begins execution. In this way, useful work is performed while the time-consuming operation is completed     

Robust Multithreaded Object Tracker through Occlusions for Spatial Augmented Reality

A spatial augmented reality (SAR) system enables a virtual image to be projected onto the surface of a real-world object and the user to intuitively control the image using a tangible interface. However, occlusions frequently occur, such as a sudden change in the lighting environment or the generation of obstacles. We propose a robust object tracker based on a multithreaded system, which can track an object robustly through occlusions. Our multithreaded tracker is divided into two threads: the detection thread detects distinctive features in a frame-to-frame manner, and the tracking thread tracks features periodically using an optical-flow-based tracking method. Consequently, although the speed of the detection thread is considerably slow, we achieve real-time performance owing to the multithreaded configuration. Moreover, the proposed outlier filtering automatically updates a random sample consensus distance threshold for eliminating outliers according to environmental changes. Experimental results show that our approach tracks an object robustly in real-time in an SAR environment where there are frequent occlusions occurring from augmented projection images.     

硬件多线程处理器的动态功耗控制方法

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time em-bedded system working in the low workload situation, the energy efficiency of the hard-ware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.     

Exploiting Thread‐Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler‐hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write‐back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single‐instruction multiple‐data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32‐bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2‐way MLEP and 33.7% faster with a 4‐way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.     

Achieving Programming Model Abstractions for Reconfigurable Computing

This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models-and access to these computational models via high level languages-focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hardware removes the potential bottleneck of routing all system service requests through a central CPU.     

W3C Speech Interface Languages: VoiceXML [Standards in a Nutshell]

VoiceXML is the most popular language for specifying audio user interfaces for Web applications, if you have ever called an automatic telephone system to reserve an airline ticket, to trade stock, or to reach an individual or department of a large company, then you have likely used a VoiceXML application. VoiceXML is part of the World Wide Web Consortium (W3C) speech interface languages (SILs), which are extended markup languages (XML) and are widely used for developing applications that speak and listen to people. In what follows, we discuss the main features, architecture, and applications of SILs with a focus on the VoiceXML language     

Improving Error Tolerance for Multithreaded Register Files

Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.     

Multilingual spoken language processing

In the past decade, the performance of spoken language understanding systems has improved dramatically, including speech recognition, dialog systems, speech summarization, and text and speech translation. This has resulted in an increasingly widespread use of speech and language technologies in a wide variety of applications. With more than 6,900 languages in the world and the current trend of globalization, one of the most important challenges in spoken language technologies today is the need to support multiple input and output languages, especially if applications are intended for international markets, linguistically diverse user communities, and nonnative speakers. In many cases these applications have to support even multiple languages simultaneously to meet the needs of a multicultural society. Consequently, new algorithms and tools are required that support the simultaneous recognition of mixed-language input, the summarization of multilingual text and spoken documents, the generation of output in the appropriate language, or the accurate translation from one language to another. This article surveys significant ongoing research programs as well as trends, prognoses, and open research issues with a special emphasis on multilingual speech processing as described in detail in the work of Schultz and Hirschberg (2006) and multilingual language processing as presented in the work of Fung (2006).     

适用于嵌入式应用的多线程顶点处理器设计

针对嵌入式应用中三维图形渲染的要求,设计了一款可编程的多线程顶点处理器.该顶点处理器采用单指令多数据结构,一条指令能够同时处理4个单精度浮点数,并采用多线程技术,支持4个线程并发执行,能够有效地减少发生数据写读冲突时的停顿周期数,提高了处理效率.相对于单线程结构,4线程顶点处理器在较小的硬件开销下,可以实现2.1～2.8倍的性能提升.该顶点处理器支持OpenGL ES 1.1和Vertex Shader Model 1.1,在90nm CMOS工艺库下可实现频率为200MHz,性能为50Mvertices/s.     

Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs

Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language—a language for specifying DSP-oriented dataflow graphs—with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.     

Ties that bind

VHDL designers can take advantage of the advanced verification features of SystemVerilog thanks to the bind function in the newer language. One of the most important languages to emerge for advanced design and verification is SystemVerilog. This language offers a rich set of features for testbench automation, applying native assertions, functional coverage and constrained random test generation. These features make SystemVerilog increasingly appealing to VHDL users who have a number of verification-oriented features at their disposal but need to implement a more efficient functional verification methodology for complex designs     

Collection-oriented languages

The authors outline, compare, and contrast the collections and operations found in many collection-oriented languages by putting them into a common framework. In the process, many problems that can occur in specifying such languages are elucidated. These languages are ideal for use with massively parallel machines, even though many of them were developed before parallelism. Some extended examples of collection operations in several languages are given. A taxonomy of collections is introduced. Issues examined include the type of elements a collection can contain, whether a collection must be homogeneously typed, and the ordering among the elements of a collection. The apply-to-each form in collection-oriented languages is examined. This form applies a function to each element of a collection. Issues treated include whether the extension of a function over the elements is explicit or implicit and how the extension is applied to functions with multiple arguments. A variety of languages (including APL, SETL, CM-Lisp, Paralation Lisp, and Fortran 90) are critically compared     

What Is the Right Organization Struture?

What are the advantages to managers in using the design decision tree? There appear to be several: 1. It provides a broad framework for identifying the key factors a manager should think about in considering an organizational design. For example: What is our environment? What different structural options do we have? 2. It forces the manager to diagnose the decision environment. What is our environment like? How stable is it? How complex is it? Is it possible to reduce complexity by segmenting the environment into product or geographical subgroups? 3. It causes managers to think about how much interdependence there is among segments of the organization. How dependent on one another are different parts of the organization in terms of technology, services, support, help in getting their tasks completed? The decision points in the heuristic forces managers to questions themselves about what other parts of the organization they need to coordinate their activities with, and then to think about how to do it. 4. Once the organization is in either a functional or decentralized structure, the decision tree points out what can be done to meet the increased needs for information through the use of lateral relations. Lateral relations provide a mechanism for supplementing the existing structure to facilitate dealing with the organization's increased needs for information and coordination. Managers in a variety of organizations have commented that the decision tree gives them ". . .     

The impact of abstraction concerns on modern programming languages

The major issues of modern software are its size and complexity, and its major problems involve finding effective techniques and tools for organization and maintenance. This paper traces the important ideas of modern programming languages to their roots in the problems and languages of the past decade and shows how these modern languages respond to contemporary problems in software development. Modern programming's key concept for controlling complexity is abstraction-that is, selective emphasis on detail; new developments in programming languages provide ways to support and exploit abstraction techniques.     

SeSFJava harness: service and assertion checking for protocol implementations

Many formal specification languages and associated tools have been developed for network protocols. Ultimately, formal language specifications have to be compiled into a conventional programming language and this involves manual intervention (even with automated tools). This manual work is often error prone because the programmer is not familiar with the formal language. So our goal is to verify and test the ultimate implementation of a network protocol, rather than an abstract representation of it. We present a framework, called services and systems framework (SeSF), in which implementations and services are defined by programs in conventional languages, and mechanically tested against each other. SeSF is a markup language that can be integrated with any conventional language. We integrate SeSF into Java, resulting in what we call SeSFJava. We present a service-and-assertion checking harness for SeSFJava, called SeSFJava harness, in which distributed SeSFJava programs can be executed, and the execution checked against services and any other correctness assertions. The harness can test the final implementation of a concurrent system. We present an application to a data transfer service and sliding window protocol implementation. SeSFJava and the harness has been used in networking courses to specify and test transmission control protocol-like transport protocols and service.     

Ontologies: giving semantics to network management models

The multiplicity of network management models may imply in some scenarios the use of multiple management information languages defining the resources to be managed. Each language has a different level of semantic expressiveness, which is not easily measurable. Also, these management information models cannot be easily integrated due to the difficulty of translation of the semantics they contain. The article proposes the use of ontologies as a new approach to improving the semantic expressiveness of management information languages. Ontologies are currently used, for instance, to provide Web pages and Web services the semantics they usually lack (known today as the semantic Web). Applying ontologies to management information languages can also be useful for integration of information definitions specified by different management languages and adding behavior information to them.     

Modeling technology impact on cluster microprocessor performance

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.