使用扩展逻辑效力的逻辑路径尺寸优化方法

为解决集成电路物理设计中考虑互连线影响的逻辑路径延迟优化问题,提出一个计入互连线负载的扩展的逻辑效力(ELE),并针对ELE给出一个可同时优化逻辑路径中各个逻辑门尺寸及各段互连线长度的优化流程.ELE在保留原有逻辑效力参数的同时,使用互连寄生参数提取软件获得的Ⅱ型互连线参数,实现对带有互连线负载的逻辑门的传播延迟的描述和估计;逻辑路径优化流程采用效力延迟分配策略作为初始条件来表示各段互连线负载对总效力延迟的影响,将所用目标单元库和制造工艺的物理尺寸信息作为限制条件,以ELE表达式为核心展开优化计算,辅以动态规划办法,无需迭代运算,仅通过一轮计算即可求得全部结果.实验结果表明,该流程计算任务简单,资源耗费少,可以准确、快速地获得所需的逻辑门尺寸和互连线长度;结果清晰合理,与目标单元库和工艺库完全兼容.     

集成电路互连延迟问题的研究及对策

随着深亚微米集成电路的发展,互连延迟现象对信号完整性、功耗等的影响正在增加。本文讨论了影响互连线延迟的因素,并讨论了从降低信号摆幅、改变开关阈值方面解决延迟、功耗等问题。     

互连线延迟评估的概率解释算法

集成电路设计工艺达到深亚微米领域时，互连线的延迟影响越来越大，已经超过门延迟，成为电路延迟的主要部分。因此，设计前期的互连线延迟的评估已成为集成电路设计中必须解决的问题。目前，已经提出了许多互连延迟的评估分析方法。本文主要介绍采用概率解释算法的原理及具体实现，并比较各自的优缺点。     

树状结构多芯片组件互连网络延迟的研究

大多芯片组件互连传输线的电路模型中,必须同时考虑线电感和线电阻,因此其互连延迟的研究比传统的ＰＣＢ和ＩＣ互连更具复杂性。研究了具有树状拓扑结构的ＭＣＭ互连网络的延迟：在明确了ＭＣＭ互连延迟的独特点后,着重给出了树状结构互连网络冲激响应的矩的求法,从矩与延迟的密切关系中给出了求延迟的一种有效方法。     

基于HVCMOS工艺的H桥驱动电路版图设计

介绍了基于HVCMOS工艺的低成本、高集成度、强驱动性能功率集成电路(Power IC,PIC)H桥的设计实现。建立的金属互连线评估模型可在设计早期对H桥物理版图方案进行优差性判断,不依赖设计后仿真,从而提高设计效率。H桥不同互连线设计方案的比较结果表明,多插指阵列器件互连线(M2及以上层金属)与器件本体的金属层M1垂直、梯形状互连结构,能够提高互连线沿电流流向的有效长宽比,减小寄生电阻。     

集成电路互连线寿命的工艺缺陷影响分析

在深亚微米和超深亚微米集成电路中,互连线失效是影响集成电路可靠性的主要因素之一。由于在集成电路制造过程中存在着缺陷,缺陷的出现导致了集成电路可靠性的下降,尤其是出现在互连线上的丢失物缺陷加剧了互连线的电迁移效应,因此电迁移失效依然是其主要的失效模式,文中讨论了电路的互连线的寿命模型,分析了丢失物缺陷以及刻蚀工艺的扰动对互连线宽度的影响,提出了新的互连线寿命估计模型．该模型还考虑了线宽、线长和缺陷峰值粒径等因素对导线寿命的影响．利用该模型可以估算出受丢失物缺陷以及刻蚀工艺扰动影响的互连线的寿命变化情况,这对IC电路设计有一定的指导作用．文中还利用模拟实验证明了该模型的有效性。     

Crossbar总线与共享总线相结合的SoC系统级通信综合方法研究

提出了一种Crossbar总线与共享总线相结合的SoC系统级通信综合方法.从实际应用的系统级设计出发,根据待互连处理单元和存储单元之间的通信量,综合出Crossbar总线与共享总线相结合的总线拓扑结构.采用遗传算法,以实际应用的通信延迟为约束,考虑总线竞争、通信同步带来的通信延迟,综合出满足延迟约束的总线参数.对综合后的Crossbar总线与共享总线进行事务级建模和分析,进一步优化生成的总线拓扑结构.实验证明,该方法解决的问题较以往更加全面,生成的总线拓扑结构和参数更优.     

集群高速互连网络分析

集群是当今高性能计算领域的重要发展方向,高速互连网络是构建高性能集群系统的关键技术,它是影响集群系统整体性能的关键因素.本文对几种用于集群互连的高带宽、低延迟高速互连网络进行了分析与比较,最后指出了高速互连网络的未来发展.     

面向互连的综合策略

VDSM(超深亚微米)设计中互连线延迟已在电路延迟中起到决定性作用。在前期设计阶段考虑互连延迟问题已是当前研究的重要课题。建立以互连为中心的综合方法是当前的一个棘手问题,尚未有成熟的方法。文章提出了一种面向互连延迟的综合策略,将前期设计定时规划,前期设计的线网规划和布局规划方法相融合,并在不同阶段给出了不同精度和复杂度的定时分析模型。文中还给出了一个设计实例对该文的综合策略予以了说明。     

低噪声高分辨IC测试系统设计

集成电路(IC)测试要求高速、高分辨率、高信噪比的信号采集系统,设计一套合适的采集系统具有极其重要的意义.论文分析了IC测试系统的组成原理,设计了低噪声信号调理电路并分析噪声系数;设计了可调相位延迟的时钟采样电路,有效实现低抖动的延迟;分析了误差对系统的影响,建立时间交替采样模型,有效校正了误差.测试表明,系统可有效实现高速高分辨的IC采集系统,达到16位分辨率、1 G采样率,波形误差达到63 dB,有效位数达到近12位,达到设计的要求.     

Rethinking deep-submicron circuit design

Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs     

Electrical analysis of single-walled carbon nanotube as gigahertz on-chip interconnects

The single-walled carbon nanotube (SWCNT) is a promising nanostructure in the design of future high-frequency system-on-chip, especially in network-on-chip, where the quality of communication between intellectual property (IP) modules is a major concern. Shrinking dimensions of circuits and systems have restricted the use of high-frequency signal characteristics for frequencies up to 1000 GHz. Four key electrical parameters, impedance, propagation constant, current density, and signal delay time, which are crucial in the design of a high-quality interconnect, are derived for different structural configurations of SWCNT. Each of these parameters exhibits strong dependence on the frequency range over which the interconnect is designed to operate, as well as on the configuration of SWCNT. The novelty of the proposed model for solving next-generation high-speed integrated circuit (IC) interconnect challenges is illustrated, compared with existing theoretical and experimental results in the literature.     

Optimization of high-speed VLSI interconnects: A review (invited article)

Today's electronic systems such as computers and digital communication systems, have necessitated a rapid increase in operating frequency. Because of this, VLSI interconnects have become one of the critical issues in an overall system design. Improperly designed interconnects lead to signal integrity degradations such as signal delay, cross talk and ground noise, limiting the overall system performance. In recent years, research into the interconnect optimization problem has been very active, and much important progress has been made. This article presents a review of the current status of this subject area. The formulations of signal-integrity oriented optimization of interconnects at different levels of electronics systems, that is; chip, multichip module (MCM), and printed circuit board (PCB) levels, are reviewed, together with various optimization techniques. Highlights on parallel and multilevel optimization for interconnect networks and the use of macromodeling techniques are also presented. Advanced formulations of interconnect optimizations featuring manufacturability oriented and multidisciplinary design objectives are reviewed. A discussion on the future challenges in the area is included at the end. © 1997 John Wiley & Sons, Inc. Int J Microwave Millimeter-Wave CAE 7: 83–107, 1997.     

一种新型FPGA器件延时计算方法

在深亚微米工艺条件下,被广泛使用的Elmore模型明显高估FPGA互连线延时;通过对RC电路冲激响应的研究,提出了采用前3阶矩确立主极点模型来计算FPGA连线延时的方法;该方法实现了计算精度和计算复杂性的折中,理论上证明该方法适用于任何结构RC电路,并且小于Elmore延时;实验表明,该方法对于远端节点估计的延时值和Spice仿真值相差不到1％;应用于商用FPGA,计算所得互连线延时的平均误差小于Elmore模型的三分之一。     

IEEE1149.4测试系统的研究与设计

分析了符合IEEE1149.4标准IC的工作机制及其对测试系统的功能需求,设计了符合IEEE1149.4标准的测试系统,重点论述了IEEE1149.4测试系统的设计方案。测试系统的仿真和运行表明,该系统具有对系统级、PCB级和芯片级电路进行简单互连测试、差分测试和参数测试等功能,设计方案正确,结构简单。     

Demystifying 3D ICs: the pros and cons of going vertical

This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.     

Delay defect characteristics and testing strategies

Several factors influence production delay testing and corresponding DFT techniques: defect sources, design styles. ability to monitor process characteristics, test generation time. available test time, and tester memory. We present an overview of delay defect characteristics and the impact of delay defects on IC quality. We also discuss practical delay-testing strategy in terms of test pattern generation, test application speed, DFT, and test cost.     

The TH Express high performance interconnect networks

Interconnection network plays an important role in scalable high performance computer (HPC) systems. The TH Express-2 interconnect has been used in MilkyWay-2 system to provide high-bandwidth and low-latency interprocessor communications, and continuous efforts are devoted to the development of our proprietary interconnect. This paper describes the state-of-the-art of our proprietary interconnect, especially emphasizing on the design of network interface. Several key features are introduced, such as user-level communication, remote direct memory access, offload collective operation, and hardware reliable end-to-end communication, etc. The design of a low level message passing infrastructures and an upper message passing services are also proposed. The preliminary performance results demonstrate the efficiency of the TH interconnect interface.