A high-speed-retry banyan switch architecture for giga-bit-rate BISDN networks

This paper proposes a high-speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross-connect system. The proposed switch architecture, named the high-speed-retry banyan switch, employs a bufferless banyan network between input and output buffers; a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell-retransmission algorithm, is employed as is a ring-arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless highspeed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high-speed-retry banyan switch. The prototype system, even in its present state, could be used to realize a giga-bit-rate BISDN switching system.     

An ultrafast photonic ATM switch based on bit-interleavemultiplexing

An optical ATM switch is proposed in which cells from individual input channels are time-division multiplexed in a bit-interleave manner. This switch can easily handle multicast switching because it is based on a broadcast-and-select network. Compared to an alternative switch that uses a cell-interleave time-division multiplexing scheme, the proposed optical switch has a much simpler structure. It does not need a cell compressor at each input and a cell expander at each output, which greatly reduces hardware complexity. Feasibility analyzes showed that a 64×64 photonic ATM switch with 2.5 Gb/s input/output is possible using the proposed technology. In an experimental demonstration, 4 b cells were selected from a 55 Gb/s bit-interleave multiplexed cell stream by using a new nonlinear optical fiber switch. With its high switch throughput, our switch is a strong candidate for future large-capacity optical switching nodes     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

Ultrafast photonic ATM switch with optical output buffers

An ultrafast photonic asynchronous transfer mode (ATM) (ULPHA) switch based on a time-division broadcast-and-select network with optical output buffers is presented. The ULPHA switch has an ultra-high throughput and excellent traffic characteristics, since it utilizes ultrashort optical pulses for cell signals and avoids cell contentions by novel optical output buffers. Feasibility studies show that an 80×80 ULPHA switch with 1-Gb/s input/output is possible by applying the present technology, and that more than 1 Tb/s is possible by making a three-stage network using such switches. As an experimental demonstration, 4-bit 40-Gb/s optical cells were generated and certain cells were selected at an output on a self-routing basis. With its high throughput and excellent traffic considerations, the ULPHA switch is a strong candidate for a future large-capacity optical switching node     

An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

All-optical packet compression of variable length packets from 40 to 1500 B using a gated fiber loop

A scalable loop-based packet compression scheme capable of handling variable length Internet protocol packets, from 40 to 1500 B, is proposed and demonstrated. The technique uses per packet variable compression ratio to achieve fixed compressed output packet size independent of input packet size. This technique allows variable length packets to be stored in fixed delay optical buffers and has application to optical packet switching, optical multiplexing, and optical grooming. These results demonstrate the largest packet size compressed to date. Error-free compression and verification of 1500-B packets compression from 2.5 to 10 Gb/s is demonstrated with a measured power penalty of /spl sim/2.2 dB.     

A 10-Gb/s high-isolation, 16×16 crosspoint switch implementedwith AlGaAs/GaAs HBT's

A high-isolation, 16×16 crosspoint switch is reported, capable of aggregate data throughput of 160 Gb/s with low crosstalk and output jitter. Each of the 16 fully asynchronous channels can transmit data at rates up to 10 Gb/s with a worst case r.m.s. output jitter of 4 ps. Single channel operation output jitter below 2.8 ps r.m.s. has been demonstrated. The high-isolation circuitry allows for inter-channel crosstalk isolation of more than 40 dB with all channels operative. The circuit is based on AlGaAs/GaAs heterojunction bipolar transistor technology     

Large-scale WDM star-based photonic ATM switches

This paper describes the large-scale photonic asynchronous transfer mode (ATM) switching systems being developed in NTT Laboratories. It uses wavelength division multiplexing (WDM) techniques to attack 1 TB/s throughput. The architecture is a simple star with modular structure and effectively combines optical WDM techniques and electrical control circuits. Recent achievements in important key technologies leading to the realization of large-scale photonic ATM switches based on the architecture are described. We show that we can obtain a 320 Gb/s system that can tolerate the polarization and wavelength dependencies of optical devices. Our experiments using rack-mounted prototypes demonstrate the feasibility of our architecture. The experiments showed stable system operation and high-speed WDM switching capability up to the total optical bandwidth of 12.8 nm, as well as successful 10 Gb/s 4×4 broadcast-and-select and 2.5 Gb/s 16×16 wavelength-routing switch operations     

Crosspoint switch equipped with an interface for serial opticalinterconnection

A crosspoint switch was developed that has an interface for serial optical interconnection. By using optoelectronic devices, cascaded switching was achieved through serial optical interconnection up to a bit rate of 10 Gb/s     

High-performance and low-consumption 10 Gb/s GaAs PHEMT driver for external modulation transmitter

This letter describes the realization of a high-performance GaAs PHEMT driver for 10 Gb/s transmitter with external coding in long haul optical transmission systems. It is shown that with an appropriate design for both IC and packaging, gain up to 14 dB, 2.5 Vp-p output drive-voltage and 1.5 W power consumption can be achieved, with adequate switching times for bit rates up to 12.5 Gb/s. The module has been successfully tested with a 18 GHz bandwidth polarization-independant pigtailed MQW electroabsorption modulator.     

Asynchronous transfer mode switching LSI chips with 10-Gb/s serialI/O ports

LSI chips were developed that fit on a switching fabric using chip-to-chip optical interconnections; they have 10-Gb/s serial input and output ports, which facilitates the layout of optically interfaced switching element modules. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors. Ultrahigh-speed switching LSI chips have been developed for a future asynchronous transfer mode (ATM) switching system with an over-Tb/s capacity. Their serial input and output ports facilitate chip-to-chip optical interconnection. Cell-dropper and crosspoint-router LSI chips, composing the core of the switching element, were fabricated by using GaAs LSI technology. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors     

Recipe for intensity modulation reduction in SOA-based interferometric switches

This paper presents a theoretical and experimental analysis of saturated semiconductor optical amplifier (SOA)-based interferometric switching arrangements. For the first time, it is shown that such devices can provide enhanced intensity modulation reduction to return-to-zero (RZ) formatted input pulse trains, when the SOA is saturated with a strong continuous-wave (CW) input signal. A novel theoretical platform has been developed in the frequency domain, which reveals that the intensity modulation of the input pulse train can be suppressed by more than 10 dB at the output. This stems from the presence of the strong CW signal that transforms the sinusoidal transfer function of the interferometric switch into an almost flat, strongly nonlinear curve. This behavior has also been verified experimentally for both periodically and randomly degraded, in terms of intensity modulation, signals at 10 Gb/s using the ultrafast nonlinear interferometer as the switching device. Performance analysis both in the time and frequency domains is demonstrated, verifying the concept and its theoretical analysis.     

13 Gb/s Si-bipolar AGC amplifier IC with high gain and wide dynamicrange for optical-fiber receivers

A complete linear automatic-gain-control (AGC) amplifier for a 10 Gb/s optical-fiber link was integrated on a single chip, using a Si-bipolar production technology with f_T≈22 GHz. It is characterized by a high gain of 37 dB, linear operation over a wide input dynamic range of 47 dB, a maximum data rate of 13 Gb/s, and a gain-independent 3-dB cut off frequency of 10 GHz. The circuit consumes 850 mW at a single supply voltage of -6.5 V. It can be operated in both a single-ended and differential mode. A novel 50-Ω input matching circuit with only small return loss is used. Two separate output buffers with a constant output voltage swing of 500 mV_p-p allow splitting up the output signal without use of external components     

Buffer sizing in an ATM switch for both ATM and STM traffics

Specific queueing models are derived in order to size the buffers of ATM switching elements in the cases of ATM or STM multiplexed traffic. Buffering is performed either at the outputs or in a central memory for ATM multiplexed traffic; for STM multiplexed traffic, buffers can also be provided at the inputs. The buffer size is chosen in order to ensure a loss probability in the switch smaller than 10^?10. It is shown that the buffer size per output in the case of central queueing is smaller than the buffer size in case of output queueing for both ATM and STM multiplexed traffics. Moreover, for STM multiplexed traffic, buffer sizes are identical for input and output queueing. Lastly, it is pointed out that buffers used for STM multiplexed traffic should be 4 to 20 times larger than the corresponding buffers for ATM multiplexed traffic.     

Rerouting network: a high-performance self-routing switch forB-ISDN

A high-performance self-routing switch is proposed for ATM (asynchronous transfer mode) switch systems. Switching performance is enhanced by a rerouting algorithm applied to a particular multistage interconnection algorithm. The interconnection algorithm offers many access points to the output and resolves output contention by layering buffers at each switching stage. The author analyzes switching performance and shows that this switch can be easily engineered to have high throughput and low cell loss probability by increasing the number of switching stages. The author also illustrates that the number of switching stages required for a given cell loss probability shows gradual growth with increasing switch size. Analysis shows that the proposed switch is robust even with respect to nonuniform traffic     

Terahipas: a modular and expandable terabit/second hierarchicallymultiplexing photonic ATM switch architecture

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's)     

CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s     

Dynamic Properties of a WDM Switching Module Based on Active Microring Resonators

The switching properties of a resonator consisting of two serially cascaded active microrings (MRs) are reported. The switching is achieved through the variation of the refractive index and the losses of the MRs with current injection, which alters the overall output spectral response. The switch is suitable for optical burst switching systems and metro architectures as it provides fast optical switching in the nanosecond scale with contrast ratio higher than 30 dB for 10-Gb/s intensity modulated signals. The capacity of the switch can be remarkably increased if multiwavelength switching is employed.