A programmable analog CMOS synapse for neural networks

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x–y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-m, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.     

Novel CMOS sampled-data VLSI implementation of artificial neural networks

A mixed-mode VLSI implementation of artificial neural networks offers a tradeoff solution for speed, area saving, and flexibility. A novel CMOS sampled-data programmable synapse and a simple CMOS analogue neuron have been developed. Using a 1.2 mu m CMOS technology, the synapse consumed 120*120 mu m/sup 2/ and the neuron consumed 120*260 mu m/sup 2/.<>     

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure     

A low-power synapse/neuron cell for artificial neural networks

A reconfigurable low-voltage low-power cell that can function either as a synapse or a neuron is proposed and analyzed in this article for the VLSI implementation of artificial neural networks (ANNs). The measured results are also presented. The design is based on the current-mode approach and uses the square-law characteristics of an MOS transistor working in saturation. The proposed fabricated synapse/neuron cell utilizes I–V converters, current mirror, and a ±1 V power supply to achieve superior performance. Modularity, ease of interconnectivity, expandability and reconfigurability are the main advantages of this cell.     

VLSI implementation of pulse activated synapses

A generic circuit, the pulse stimulated charge pumping (PSCP) synapse, is presented. The PSCP synapse is a device based on charge pumping of interface states: it produces at its output a charge packet proportional to the number of pulses applied to its input, and to the electrically programmed density of interface states. It is particularly suitable for realising artificial neural networks in which the neuron activity is implemented as a pulse train, closely resembling the behaviour of biological neural networks. The PSCP synapse can be realised easily in less than 50 mu m/sup 2/, and has a large dynamic range. Preliminary experimental results are presented showing the current against frequency behaviour of the device, for various densities of interface states.<>     

Synchronization and chaos in coupled memristor-based FitzHugh-Nagumo circuits with memristor synapse

The memristor has drawn a significant interest in the fields of neuromorphic circuits because the nanoscale memristor is a strong candidate to become the critical element of novel ultra-high density low-power non-volatile memories. In the present paper, we focus on networks of FitzHugh-Nagumo neuron circuits employing memristor. First, we build the memristor-based circuit of FitzHugh-Nagumo model. The details of the chaotic phenomena of the memristor-based FitzHugh-Nagumo circuit under external stimuli have been found with use of computer simulations, i.e., we have numerically calculated waveform diagrams, phase portraits, Lyapunov exponents and bifurcation diagram. And we also confirm these results of theoretical analyses and numerical calculations by circuit simulation experiments of the actual analog circuit realization using Multisim modeling. Then the synchronization of coupled memristor-based chaotic neurons with memristor synapse is discussed, and synchronization mechanism is also found. Finally, we have also derived the sufficient conditions of chaotic synchronization in unidirectional coupled neuron circuits and bidirectional coupled neuron circuits respectively, which are that the parameter of memristor synapse must meet certain conditions. These results of theoretical analyses have been confirmed by numerical simulation.     

一个脉冲发放型人工神经元

本文首先总结了生物神经元的一些基本特性,对调节联接的霍伯(Hebb)规则提出了新的见解,得出生物神经元的总和过程是间歇式的结论,通过对支配神经元活动的Hodgkin-Huxley方程进行合理简化得到一个具有类似于生物神经元动作方式的人工神经元;给出了这一模型的电路实现和解析解 ;最后,研究了该模型组成的多层网络实现异或分类问题.该模型具有生物神经元的主要特性,如总和效应、潜伏期和不应期等,并且兼顾到在工程上其容易由硬件、软件实现等问题.     

Low power building block for artificial neural networks

The authors propose and analyse a low-power CMOS building block for artificial neural networks (ANNs) that can function either as a synapse or a neuron. The design is based on the current-mode approach and uses the square-law characteristics of a MOS transistor working in saturation. The new building block uses I-V converters, a current-mirror and a ±1 V power supply to achieve superior performance. Modularity, ease of interconnectivity, expandability and reconfigurability are the advantages of this building block     

A MODEL OF NEURAL CIRCUIT WITH ADAPTION AND NONLINEAR CONNECTION

Based on physiological properties of synapse, soma and axon, this paper presents and analyses a model of neural circuit which can approximately simulate input-output relation, strength-duration curve, adaption and nonlinear connection of real neuron. The obtained results show that the model approximates to realistic principles of neural computation better than the available neural networks. The impulse-coded WTA(winner takes all) networks constructed with the above model find the winner more effectively than the analog WTA. Finally, the two important concepts: time competition and strength competition are introduced, which illustrate that the model has abilities to perform series and parallel information processing.     

Implementation of new superconducting neural circuits using coupledSQUIDs

A novel superconducting neuron circuit and two types of variable synapses, which are based on superconducting quantum interferometer devices (SQUIDs), are presented. A neuron circuit with good input-output isolation and steep threshold characteristics is accomplished using a combination of a single-junction SQUID coupled to a double-junction SQUID. The quantum state of the single-junction SQUID represents the neuron state, and the output voltage of the double-junction SQUID, which is operated in a nonlatching mode with shunt resistors, is a sigmoid-shaped function of the input. Both variable synapse circuits are composed of multiple shunted double-junction SQUIDs. The first type changes its conductance value by using both superconducting and voltage states. The second variable synapse circuit changes its output current digitally by switching its bias currents. Besides numerical simulations of the circuit characteristics, we have fabricated superconducting neural chips in a Nb/AlO_x/Nb Josephson junction technology. The fundamental operation of each element and a 2-bit neural-based A/D converter have been successfully tested. A learning system with a variable synapse is also discussed     

模拟神经元电路实现研究现状与进展

人工神经网络是现代信息处理领域的一个重要的方法。相对于软件实现 ,硬件实现方式能充分发挥神经网络并行处理的特点。用模拟电路实现神经网络电路形式简单、功耗低、速度快、占用芯片面积小 ,可以提高在神经网络芯片上神经元的集成度 ,神经元电路适合用模拟电路实现。文中综述了当前神经网络单元的模拟 VLSI实现的成果、新技术以及作者的工作成果。针对应用最广泛的线性和平方突触神经元 ,详细从权值存储单元、突触电路和阈值函数电路三方面来叙述。对各种实现方式的优缺点进行了比较 ,同时指出了神经网络实现电路中需要考虑的因素。最后 ,展望了用集成电路技术实现自学习神经网络的发展方向     

Implementation of a learning Kohonen neuron based on a newmultilevel storage technique

A compact implementation of a fully parallel Kohonen network with learning capabilities is described. Implementation issues concerning general neural networks are briefly explored, and an original mixed analog and digital technique for storing discrete voltages on a capacitor is presented. The limitations are discussed, and measurements on the storage dynamics are reported, showing that 8 b of resolution can be achieved. This technique is applied to the realization of a neuron dedicated to Kohonen maps. This neuron has been implemented in a standard 2-μm CMOS technology, and the synaptic functions are very dense. The implementation uses a standard 8-b integer arithmetic. Efficient and consistent encoding of the information, dynamic storage, and the adaptation of the synaptic weights and the synaptic multipliers use simple circuitry, thus leading to a low number of transistors     

RBF神经网络在视频业务建模及预测中的应用

ＡＴＭ技术在关键在于业务控制,能否有效地实施业务控制则取决于对业务特征的了解和预测能力。传统的解析方法对视频业务进行预测的局限性较为明显。本文采用径向基函数神经网络对视频业务进行建模和预测,并提出了分别采用ＬＢＧ算法和Ｈｅｓｔｅｎｅｓ奇异值解进行隐含层神经元中心选择和输出神经腱权值计算的改进方法。     

局部有源忆阻器电路及其在HR耦合神经元网络中的应用

该文提出一种新型局部有源忆阻器,使用标准非线性理论分析方法分析其特性,并通过直流伏安特性曲线来证明其局部有源性。此外,将局部有源忆阻器用于模拟生物突触,构建了一个局部有源忆阻突触耦合HR神经元网络。理论分析和数值仿真表明,在局部有源忆阻突触的影响下它能够产生多种放电模式和复杂的混沌行为。最后,实现了该局部有源忆阻突触耦合神经网络的模拟等效电路,并由功率模拟(PSIM)电路仿真验证了数值仿真的正确性。     

Transparent and Flexible Inorganic Perovskite Photonic Artificial Synapses with Dual-Mode Operation

With the rapid development of artificial intelligence, the simulation of the human brain for neuromorphic computing has demonstrated unprecedented progress. Photonic artificial synapses are strongly desirable owing to their higher neuron selectivity, lower crosstalk, wavelength multiplexing capabilities, and low operating power compared to their electric counterparts. This study demonstrates a highly transparent and flexible artificial synapse with a two-terminal architecture that emulates photonic synaptic functionalities. This optically triggered artificial synapse exhibits clear synaptic characteristics such as paired-pulse facilitation, short/long-term memory, and synaptic behavior analogous to that of the iris in the human eye. Ultraviolet light illumination-induced neuromorphic characteristics exhibited by the synapse are attributed to carrier trapping and detrapping in the SnO₂ nanoparticles and CsPbCl₃ perovskite interface. Moreover, the ability to detect deep red light without changes in synaptic behavior indicates the potential for dual-mode operation. This study establishes a novel two-terminal architecture for highly transparent and flexible photonic artificial synapse that can help facilitate higher integration density of transparent 3D stacking memristors, and make it possible to approach optical learning, memory, computing, and visual recognition.     

采用脉冲宽度调制技术实现人工神经网络

该文提出了一种采用脉冲宽度调制(PWM)技术实现的人工神经网络(ANN),神经网络的权值采用数字存储器存储,突触电路由开关组成,电容积分电路和电流采样保持电路完成输入信号和权值信号的乘加运算,输出采用双电流镜。电路结构简单,易于集成,可用于构成前馈网络,如实现异或运算的人工神经网络。     

A Mixed-Mode Analog Neural Network Using Current-Steering Synapses

A hardware neural network is presented that combines digital signalling with analog computing. This allows a high amount of parallelism in the synapse operation while maintaining signal integrity and high transmission speed throughout the system. The presented mixed-mode implementation achieves a synapse density of 4 k per mm² in 0.35 μm CMOS. The current-mode operation of the analog core combined with differential neuron inputs reaches an analog precision sufficient for 10 bit parity while running at a speed of 0.8 Teraconnections per second.     

A reconfigurable VLSI neural network

Due to the variety of architectures that need be considered while attempting solutions to various problems using neural networks, the implementation of a neural network with programmable topology and programmable weights has been undertaken. A new circuit block, the distributed neuron-synapse, has been used to implement a 1024 synapse reconfigurable network on a VLSI chip. In order to evaluate the performance of the VLSI chip, a complete test setup consisting of hardware for configuring the chip, programming the synaptic weights, presenting analog input vectors to the chip, and recording the outputs of the chip, has been built. Following the performance verification of each circuit block on the chip, various sample problems were solved. In each of the problems the synaptic weights were determined by training the neural network using a gradient-based learning algorithm which is incorporated in the experimental test setup. The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently     

A Gaussian synapse circuit for analog VLSI neural networks

Back-propagation neural networks with Gaussian function synapses have better convergence property over those with linear-multiplying synapses. In digital simulation, more computing time is spent on Gaussian function evaluation. We present a compact analog synapse cell which is not biased in the subthreshold region for fully-parallel operation. This cell can approximate a Gaussian function with accuracy around 98% in the ideal case. Device mismatch induced by fabrication process will cause some degradation to this approximation. The Gaussian synapse cell can also be used in unsupervised learning. Programmability of the proposed Gaussian synapse cell is achieved by changing the stored synapse weight W_ji, the reference current and the sizes of transistors in the differential pair     

血管性痴呆小鼠海马神经元超微病理特征研究

目的：探讨血管性痴呆(VD)小鼠海马神经元超微病理特征及其变化的意义。方法：采用双侧颈总动脉线结、反复缺血—再灌注法,制作小鼠VD动物模型。取两组小鼠海马组织制成超薄切片,透射电镜观察。结果：(1)假手术组：海马神经元和神经毡结构均正常。(2)VD模型组：海马神经元核肿胀、有局部凹陷现象;核周体细胞器明显减少,多聚核糖体稀散;仅残留受到破坏的高尔基体和粗面内质网、线粒体变性。髓鞘层裂;轴突中神经微管结构模糊。神经毡中可见树突和轴突不同程度水肿,尤其是树突呈现极度扩张形成不规则的“气球”,其中含有许多大小不等的薄膜空泡。突触数量显著减少,可见穿孔和异形的突触;有的突触小泡破裂,呈片状均质化。结论：海马神经元的超微结构病变导致神经元功能异常、突触可塑性降低,可能在VD的病因中起重要作用。