碳化硅金刚线切割表面粗糙度的研究

碳化硅是新兴的第三代半导体材料。用固定磨料金刚线切割机对其进行切割加工,分析了加工过程的各项参数对晶片表面粗糙度的影响,为优化碳化硅金刚线切割过程提出依据。     

Experiment study on electroplated diamond wire saw slicing single-crystal silicon

This paper conducted the slicing experiments of single-crystal silicon using a reciprocating electroplated diamond wire saw. The machined wafer topography and wire wear were observed by using scanning electron microscope (SEM). The influences of process parameters and cutting fluids on single-crystal silicon wafer surface roughness (SR), subsurface micro-crack damage (SSD) depth, total thickness variation (TTV) and warp were investigated. The bonded interface sectioning technique was used to examine the cut wafers SSD depth. Study results show that a higher wire speed and lower ingot feed speed can produce lower wafer SR and SSD; the lower warp of wafer needs lower wire speed and ingot feed speed; and low wafer TTV can be obtained by an appropriate matching relationship between wire speed and ingot feed speed. The synthetic cutting fluid has a better total effect to improve the wafer quality. The pulled-out of diamond abrasives is the main wear form of wire, which indicates that more research on improving the abrasives retaining strength on wire surface should be investigated in fixed-abrasive wire manufacturing process, in order to improve the wire life and wire saw machining process.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

变速切割速度曲线对硅片翘曲度的影响

根据线切割机的工作原理,综合考虑了砂浆中磨料在磨削过程中的变化以及单晶直径的变化,确定了变速切割的工艺方法,同时考虑到125 mm单晶直径大、SIC磨削路线长、磨削发热量大,制定了包括线速度、耗线量、砂浆温度、砂浆流量以及各部分温度的工艺参数。通过该工艺参数进行了切割实验,验证了该工艺参数下切割的晶片可以满足要求。     

Effect of wire vibration on the materials loss in sapphire slicing with the fixed diamond wire

Sawn kerf, wafer profile error and wafer subsurface damage were systematically measured and were used to evaluate the materials loss for the sapphire slicing with the fixed diamond wire. The vibration of saw wire was also measured during the slicing process. The impact of each part on the materials loss was discussed. The effect of the wire vibration on the materials loss was explored. It was found that the sawn kerf loss and the wafer profile error loss were the main forms of the materials loss during the slicing process. Wire vibration has significant influence on sliced wafer morphology. Influence of slice parameters on the kerf loss is similar with the case on the vibration amplitude, which indicates that the wire vibration is the key factor to cause the kerf loss. Wire slicing model with the wire vibration is established to understand the influence of wire vibration on the materials loss.     

Mechanisms of wafer sawing and impact on wafer properties

Silicon wafer wire‐sawing experiments were realized with different sets of sawing parameters, and the thickness, roughness, and cracks depth of the wafers were measured. The results are discussed in relation to assumptions underlying the rolling–indenting model, which describes the process. It was also found that the silicon surface at the bottom of the sawing groove is different from the wafer surface, implying different sawing conditions in the two positions. Furthermore, the measured parameters were found to vary along the wire direction, between the entrance of the wire in the ingot and its exit. Based on these observations, some improvements for the wire‐sawing model are discussed. Copyright © 2010 John Wiley & Sons, Ltd.     

Subsurface crack damage in silicon wafers induced by resin bonded diamond wire sawing

In order to optimize the process of wire sawing, this work studied the subsurface crack damage in silicon wafers induced by resin bonded diamond wire sawing using theoretical and experimental methods. A novel mathematical relationship between subsurface crack damage depth and processing parameters was established according to the indentation fracture mechanics. Sawing experiment using resin bonded diamond wire saw was performed on a wire saw machine. The validity of the proposed model was conducted by comparing with the experimental results. At last, the influences of processing parameters on subsurface damage depth were discussed. Results indicate that the median cracks are mainly oblique cracks which generate the subsurface crack damage. On the diamond wire saw cross section, the abrasives with the position angle 78° between abrasive position and vertical direction generate the largest subsurface damage depth. Furthermore, abrasives, generating the subsurface damage, tend away from the bottom of diamond wire with the increase of wire speed or decreases with the increase of feed rate. However, the wire speed and feed rate have opposite effects on the subsurface crack damage depth. In addition, the subsurface crack damage depth is unchanged when the ratio of feed rate and wire speed does not change.     

Si片多线切割技术与设备的发展现状与趋势

介绍了Si片的多线切割宏观切割机理与微观切割机理,指出控制钢线张力减少钢线震动是切割工艺的重要指标。讨论了切割过程主要影响因素,钢线的外包Cu会造成Si片表面金属残留,钢线磨损影响Si片厚度,砂浆喷嘴和线网角度在形成水平薄膜层时能够获得好的表面质量。分析了钢线带动砂浆进行切割的核心工艺,给出了Si片切割工艺理论切片量的计算方法。并简要概括了目前多线切割技术及设备的国内外发展形势和未来发展趋势,指出未来多线切割技术将朝着提高加工精度与加工效率、降低成本、改良切割用钢线这几个方向迈进。     

Comparison of thin epitaxial film silicon photovoltaics fabricated on monocrystalline and polycrystalline seed layers on glass

We fabricate thin epitaxial crystal silicon solar cells on display glass and fused silica substrates overcoated with a silicon seed layer. To confirm the quality of hot‐wire chemical vapor deposition epitaxy, we grow a 2‐µm‐thick absorber on a (100) monocrystalline Si layer transfer seed on display glass and achieve 6.5% efficiency with an open circuit voltage (V_OC) of 586 mV without light‐trapping features. This device enables the evaluation of seed layers on display glass. Using polycrystalline seeds formed from amorphous silicon by laser‐induced mixed phase solidification (MPS) and electron beam crystallization, we demonstrate 2.9%, 476 mV (MPS) and 4.1%, 551 mV (electron beam crystallization) solar cells. Grain boundaries likely limit the solar cell grown on the MPS seed layer, and we establish an upper bound for the grain boundary recombination velocity (S_GB) of 1.6x10⁴ cm/s. Copyright © 2014 John Wiley & Sons, Ltd.     

Recovery of silicon from kerf loss slurry waste for photovoltaic applications

The constantly rising price of silicon feedstock has been the most important factor preventing photovoltaic (PV) energy from reaching grid parity. On the other hand, large amount of silicon gets wasted during slicing. We report a promising approach to recycle kerf loss silicon from cutting slurry waste for solar cell applications. Silicon carbide (SiC) and metal impurities were successfully removed by chemical/ physical processing from the slurry waste to recover solar grade silicon. The effects of centrifugation using heavy fluids and high‐temperature treatment in the removal of SiC particles are discussed in detail. Ingots from the recycled silicon were grown by using directional solidification. The average resistivity and minority carrier lifetime of the grown crystals were found to be about 0·7 Ω cm and 1·02 µs, respectively, which were close to the original sawing silicon ingots. Solar cells using multi‐crystalline wafers of recovered silicon were fabricated and the best energy conversion efficiency was found to be 12·6% comparable to those from the high‐purity silicon. Copyright © 2008 John Wiley & Sons, Ltd.     

Determination of the bulk lifetime of bare multicrystalline silicon wafers

The determination of the bulk lifetime of bare multicrystalline silicon wafers without the need of surface passivation is a desirable goal. The implementation of an in‐line carrier lifetime analysis is only of benefit if the measurements can be done on bare unprocessed wafers and if the measured effective lifetime is clearly related to the bulk lifetime of the wafer. In this work, we present a detailed experimental study demonstrating the relationship between the effective carrier lifetime of unpassivated wafers and their bulk carrier lifetime. Numerical modelling is used to describe this relationship for different surface conditions taking into account the impact of a saw damage layers with poor electronic quality. Our results show that a prediction of the bulk lifetime from measurements on bare wafers is possible. Based on these results we suggest a simple procedure to implement the analysis for in‐line inspection. Copyright © 2010 John Wiley & Sons, Ltd.     

Prediction of sawing force for single-crystal silicon carbide with fixed abrasive diamond wire saw

Fixed abrasive diamond wire saw has been used to cut hard-and-brittle materials into wafers, such as silicon carbide. The force of a single abrasive determines the cutting depth, and affects material removal mode and crack propagation length. Therefore, the sawing force is a key factor that affects the surface/subsurface quality of wafers. In this paper, a numerical sawing force predicting method considering wire saw parameters was proposed with the combination of both ductile removal and brittle fracture removal for each single abrasive. A new calculation method of single abrasive cutting force considering frictional force component and new material removal way considering the effect of lateral crack were adopted. Then the influences of process parameters and wire parameters on sawing force were analyzed. Finally, mathematical sawing force formulas described by both process parameters and wire saw parameters were obtained using the new sawing force prediction method. The validity of this prediction method and sawing force formulas was verified through experiments in the literature under the same process parameters and wire saw parameters.     

Performance enhancement of multicrystalline silicon solar cells and modules using double‐layered SiNx:H antireflection coatings

Silicon nitride coating deposited by the plasma‐enhanced chemical vapor deposition method is the most widely used antireflection coating for crystalline silicon solar cells. In this work, we employed double‐layered silicon nitride coating consisting of a top layer with a lower refractive index and a bottom layer (contacting the silicon wafer) with a higher refractive index for multicrystalline silicon solar cells. An optimization procedure was presented for maximizing the photovoltaic performance of the encapsulated solar cells or modules. The dependence of their photovoltaic properties on the thickness of silicon nitride coatings was carefully analyzed. Desirable thicknesses of the individual silicon nitride layers for the double‐layered coatings were calculated. In order to get statistical conclusions, we fabricated a large number of multicrystalline silicon solar cells using the standard production line for both the double‐layered and single‐layered antireflection coating types. On the cell level, the double‐layered silicon nitride antireflection coating resulted in an increase of 0.21%, absolute for the average conversion efficiency, and 1.8 mV and 0.11 mA/cm² for the average open‐circuit voltage and short‐circuit current density, respectively. On the module level, the cell to module power transfer factor was analyzed, and it was demonstrated that the double‐layered silicon nitride antireflection coating provided a consistent enhancement in the photovoltaic performance for multicrystalline silicon solar cell modules than the single‐layered silicon nitride coating. Copyright © 2015 John Wiley & Sons, Ltd.     

Phase transformations during the Ag-In plating and bonding of vertical diode elements of multijunction solar cells

The conditions of the bonding of silicon multijunction solar cells with vertical p-n junctions using Ag-In solder are studied. The compositions of electrodeposited indium films on silicon wafers silver plated by screen printing and silver and indium films fabricated by layer-by-layer electrochemical deposition onto the surface of silicon vertical diode cells silver plated in vacuum are studied. Studying the electrochemical-deposition conditions, structure, and surface morphology of the grown layers showed that guaranteed bonding is provided by 8-min heat treatment at 400°C under the pressure of a stack of metallized silicon wafers; however, the ratio of the indium and silver layer thicknesses should not exceed 1: 3. As this condition is satisfied, the solder after wafer bonding has the InAg₃ structure (or InAg₃ with an Ag phase admixture), due to which the junction melting point exceeds 700°C, which guarantees the functioning of such solar cells under concentrated illumination.     

>16% thin‐film epitaxial silicon solar cells on 70‐cm2 area with 30‐µm active layer,porous silicon back reflector,and Cu‐based top‐contact metallization

We demonstrate the use of a copper‐based metallization scheme for the specific application of thin‐film epitaxial silicon wafer equivalent (EpiWE) solar cells with rear chemical vapor deposition emitter and conventional POCl₃ emitter. Thin‐film epitaxial silicon wafer equivalent cells are consisting of high‐quality epitaxial active layer of only 30 µm, beneath which a highly reflective porous silicon multilayer stack is embedded. By combining Cu‐plating metallization and narrow finger lines with an epitaxial cell architecture including the porous silicon reflector, a J_sc exceeding 32 mA/cm² was achieved. We report on reproducible cell efficiencies of >16% on >70‐cm² cells with rear epitaxial chemical vapor deposition emitters and Cu contacts. Copyright © 2011 John Wiley & Sons, Ltd.     

Multi‐crystalline Si solar cells with very fast deposited (180 nm/min) passivating hot‐wire CVD silicon nitride as antireflection coating

Hot‐wire chemical vapor deposition (HWCVD) is a promising technique for very fast deposition of high quality thin films. We developed processing conditions for device‐ quality silicon nitride (a‐SiN_x:H) anti‐reflection coating (ARC) at high deposition rates of 3 nm/s. The HWCVD SiN_x layers were deposited on multicrystalline silicon (mc‐Si) solar cells provided by IMEC and ECN Solar Energy. Reference cells were provided with optimized parallel plate PECVD SiN_x and microwave PECVD SiN_x respectively. The application of HWCVD SiN_x on IMEC mc‐Si solar cells led to effective passivation, evidenced by a V_oc of 606 mV and consistent IQE curves. For further optimization, series were made with HW SiN_x (with different x) on mc‐Si solar cells from ECN Solar Energy. The best cell efficiencies were obtained for samples with a N/Si ratio of 1·2 and a high mass density of >2·9 g/cm³. The best solar cells reached an efficiency of 15·7%, which is similar to the best reference cell, made from neighboring wafers, with microwave PECVD SiN_x. The IQE measurements and high V_oc values for these cells with HW SiN_x demonstrate good bulk passivation. PC1D simulations confirm the excellent bulk‐ and surface‐passivation for HW SiN_x coatings. Interesting is the significantly higher blue response for the cells with HWCVD SiN_x when compared to the PECVD SiN_x reference cells. This difference in blue response is caused by lower light absorption of the HWCVD layers (compared to microwave CVD; ECN) and better surface passivation (compared to parallel plate PECVD; IMEC). The application of HW SiN_x as a passivating antireflection layer on mc‐Si solar cells leads to efficiencies comparable to those with optimized PECVD SiN_x coatings, although HWCVD is performed at a much higher deposition rate. Copyright © 2007 John Wiley & Sons, Ltd.     

Electron‐beam crystallized large grained silicon solar cell on glass substrate

Thin film hetero‐emitter solar cells with large‐grained poly‐silicon absorbers of around 10 µm thickness have been prepared on glass. The basis of the cell concept is electron‐beam‐crystallization of an amorphous or nanocrystalline silicon layer deposited onto a SiC:B layer. The SiC:B layer covers a commercially well available glass substrate, serving as diffusion barrier, contact layer and dopand source. For silicon absorber deposition a low pressure chemical vapour deposition was used. The successively applied e‐beam crystallization process creates poly‐silicon layers with grain sizes up to 1 × 10 mm² with low defect densities. The high electronic quality of the absorber is reflected in open circuit voltages as high as 545 mV, which are realized making use of the well‐developed a‐Si:H hetero‐emitter technology. Copyright © 2011 John Wiley & Sons, Ltd.     

多线切割机的切割运动分析

半导体晶圆不断向大直径方向发展,内圆刀具的单片切割方式已经不能满足大直径晶圆的切片要求,随着多线锯切割技术的完善,多线切割机已经是半导体材料切片的主流设备。对砂粒在切割过程中的运动进行了分析,同时对钢线张力、切削进给运动进行了理论分析。     

Light‐trapping properties of patch textures created using laser assisted texturing

For crystalline silicon solar cells, the efficient collection of light at wavelengths in the infrared is a challenge because of long absorption lengths. Especially for thinner wafers, an efficient light‐trapping scheme, such as the patch texture, is required for high short‐circuit current densities. We have measured the light‐trapping properties of patch textures produced by laser assisted texturing (LAST) on polished ⟨100⟩silicon wafers, and compared them with ray‐tracing simulations. Single‐sided random pyramid textures are created for comparison. Excellent agreement between simulations and measurements is achieved by employing diffuse scattering with a narrow angular distribution in the simulations, confirming the successful implementation of the process. We use our optical measurements of the textures for simulations of textures with rear reflectors, where we also investigate the influence on light‐trapping properties when varying geometry and reflectance properties. The results from the optical simulations are imported into the solar cell simulation program PC1D. For a 50 μm‐thick solar cell, we simulate an improvement in J_sc of up to 0.4 mA/cm² when going from single‐sided random pyramid textures to patch textures, even when the performance of the texture is limited by process inaccuracies. Removing the physical inaccuracies of the laser system, the potential gain in J_sc on a 50 μm‐thick cell with a patch texture covering the complete wafer surface is 0.8 mA/cm². We therefore conclude that the LAST method for creating patch textures is suitable to achieve an improved J_sc in thin monocrystalline silicon solar cells. Copyright © 2013 John Wiley & Sons, Ltd.     

Influence of wafer thickness on the performance of multicrystalline Si solar cells: an experimental study

The influence of the thickness of silicon solar cells has been investigated using neighbouring multicrystalline silicon wafers with thickness ranging from 150 to 325 μm. For silicon solar cell structures with a high minority‐carrier diffusion length one expects that J_sc would decrease as the wafer becomes thinner due to a shorter optical path length. It was found experimentally that J_sc is nearly independent of the thickness of the solar cell, even when the minority‐carrier diffusion length is about 300 μm. This indicates that the Al rear metallisation acts as a good back surface reflector. A decrease in J_sc is observed only if the wafer thickness becomes less than about 200 μm. The observed trend in V_oc as a function of the wafer thickness has been explained with PC1D modelling by a minority‐carrier diffusion length in the Al‐oped BSF which is small in relation to the thickness of the BSF. This effectively increases the recombination velocity at the rear of the cell. We have shown that the efficiency of solar cells made with standard industrial processing is hardly reduced by reducing the wafer thickness. Solar cell efficiencies might be increased by better rear surface passivation. Copyright © 2002 John Wiley & Sons, Ltd.