Fitted Elmore delay: a simple and accurate interconnect delay model

In this brief, we present a new interconnect delay model called fitted Elmore delay (FED). FED is generated by approximating HSPICE delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay (ED) model. Thus, our model has all the advantages of the ED model. It has a closed-form expression as simple as the ED model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the ED model. In fact, most previous algorithms and programs based on ED model can use our model without much change. Most importantly, FED is significantly more accurate than the ED model. The maximum error in delay estimation is at most 2% for our model, compared to 8.5% for the scaled ED model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than the ED model when applied to wire sizing.     

基于排队时延和丢包率的拥塞控制

作为拥塞度量,排队时延具有很多优点,但仅利用排队时延并不能完全避免丢包,而在链路缓存不足出现丢包时,排队时延已不能有效反应网络拥塞情况。该文提出了一种基于排队时延和丢包率的拥塞控制模型,该模型采用双模控制的方法。在瓶颈链路上有足够缓存时,模型利用排队时延作为拥塞度量,使各流获得稳定的动态性和成比例公平性。当瓶颈路由器上没有足够缓存不可避免要丢包时,模型利用丢包率作为拥塞度量,使各流仍能获得与不丢包情况下相近的流特性。模型在两种模式的切换中保持稳定,实现平滑过渡。     

A Comprehensive Delay Model for CMOS CML Circuits

MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-$mu{hbox {m}}$ CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.      

Modeling of cardiovascular variability using a differential delayequation

The influence of time delay in the baroreflex control of the heart activity is analyzed by using a simple mathematical model of the short-term pressure regulation. The mean arterial pressure in a Windkessel model is controlled by a nonlinear feedback driving a nonpulsatile model of the cardiac pump in accordance with the steady-state characteristics of the arterial baroreceptor reflex. A pure time delay is placed in the feedback branch to simulate the latent period of the baroreceptor regulation. Because of system nonlinearity model dynamics is found to be highly sensitive to time delay and changes of this parameter within a physiological range cause the model to exhibit different patterns of behavior. For low values of time delay (shorter than 0.5 s) the model remains in a steady state. When time delay is longer than 0.5 s, a Hopf bifurcation is crossed and spontaneous oscillations occur with frequencies in the high-frequency (HF) band. Further increases of time delay above 1.2 s cause the oscillations to become more complex, and following the typical Feigenbaum cascade, the system becomes chaotic. In this condition heart rate, pressure, and how show evident variability. The heart rate power spectrum exhibits a peak whose frequency moves from the HF to LF band depending on whether simulated time delay is as short as the vagal-mediated control or long as the sympathetic one     

Fast Interconnect and Gate Timing Analysis for Performance Optimization

Static timing analysis is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model-order reduction techniques for wire delay calculation is prohibitively expensive. In this paper, we present sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis. The key idea is to partition the circuit into low and high complexity circuits, whereby low complexity circuits are handled with efficient algorithms such as total capacitance algorithm for gate delay and the Elmore metric for wire delay and high complexity circuits are handled with sign-off algorithms. Experimental results on microprocessor designs show accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times     

Closed-Form RC and RLC Delay Models Considering Input Rise Time

The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmore's approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy.     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

An algorithm is presented for obtaining placements of cell-based very large scale integrated circuits, subject to timing constraints based on table-lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well-known quadratic placement with bottom-up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.     

Analysis of BiCMOS buffer for input voltages with finite rise time

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design     

An analytical model of delay in multi-hop wireless ad hoc networks

Several analytical models of different wireless networking schemes such as wireless LANs and meshes have been reported in the literature. To the best of our knowledge, all these models fail to address the accurate end-to-end delay analysis of multi-hop wireless networks under unsaturated traffic condition considering the hidden and exposed terminal situation. In an effort to gain deep understanding of delay, this paper firstly proposes a new analytical model to predict accurate media access delay by obtaining its distribution function in a single wireless node. The interesting point of having the media access delay distribution is its generality that not only enables us to derive the average delay which has been reported in almost most of the previous studies as a special case but also facilitates obtaining higher moments of delay such as variance and skewness to capture the QoS parameters such as jitters in recently popular multimedia applications. Secondly, using the obtained single node media access delay distribution, we extend our modeling approach to investigate the delay in multi-hop networks. Moreover, probabilities of collisions in both hidden and exposed terminal conditions have been calculated. The validity of the model is demonstrated by comparing results predicted by the analytical model against those obtained through simulation experiments.     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

There have been extensive studies on timing-driven placement in recent years.Theapproaches toward this problem fall into two main categories:net-based and path-based.In a typical net-based one,potential critical paths and acceptable d...     

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.     

基于单向传输的光纤时延波动测量

为了与现有光纤通信网络兼容,研究了一种基于单纤单向传输的光纤时延波动测量方法。基于色散温变效应和Sellmeier等式,建立了利用温度的准确测量和双波长光信号传输时延差波动反推单向时延波动的比例模型。令模型中的比例系数是单波长时延波动和双波长时延差波动的比,仿真研究了温度和波长差对比例系数的影响。搭建了75 km光纤单向时延波动测量实验平台,实验结果表明:实测比例系数?258.4接近于理论比例系数?277.3,对应单向传输时延波动误差为660 ps,实验结果验证了模型的正确性和基于单向传输的光纤时延波动测量的可能性。     

A framework for deterministic delay guarantee in OBS networks

In OBS networks, the delay of control packets in the switch control unit (SCU) of core nodes influences burst loss performance in the optical switching and should be constrained. Furthermore, the end-to-end (E2E) delay requirements of premium services need queueing delay guarantee in network nodes throughout the transmission path. For this purpose, a framework for deterministic delay guarantee is proposed in this article. It incorporates the deterministic delay model in the ingress edge node as well as in the SCUs of core nodes. On this basis, the configuration of the assembler and the offset time is addressed by means of an optimization problem under the delay constraints. Scenario studies are carried out with reference to realistic transport network topologies. Compared to statistical delay models in the literature, the deterministic model has advantages in rendering robust absolute delay guarantee for individual FEC flows, which is especially appreciated in the provisioning of premium services. By performance evaluation in comparison with the statistical models, it is shown that the adopted deterministic delay models lead to practical delay bounds in a magnitude that is close to the delay estimations by stochastic analysis.     

考虑工艺波动影响的RLC互连统计延时

该文提出了一种考虑工艺波动的统计RLC互连延时分析方法。文中首先给出了考虑工艺波动的寄生参数和矩的构建方法,然后基于Weibull分布给出了RLC互连的统计延时模型。所提方法同样适用于已有的延时模型如Elmore模型,等效Elmore模型和D2M模型。通过对几种模型的比较,表明,基于Weibull分布的RLC互连的统计延时模型是最精确的,和HSPICE相比,50%延时误差最大0.11%,蒙特卡洛分析中的均值和平均偏差误差最大2.02%。     

A stochastic model of the temporal and azimuthal dispersion seen atthe base station in outdoor propagation environments

A simple statistical model of azimuthal and temporal dispersion in mobile radio channels is proposed. The model includes the probability density function (PDF) of the delay and azimuth of the impinging waves as well as their expected power conditioned on the delay and azimuth. The statistical properties are extracted from macrocellular measurements conducted in a variety of urban environments. It is found that in typical urban environments the power azimuth spectrum (PAS) is accurately described by a Laplacian function, while a Gaussian PDF matches the azimuth PDF. Moreover, the power delay spectrum (PDS) and the delay PDF are accurately modeled by an exponential decaying function. In bad urban environments, channel dispersion is better characterized by a multicluster model, where the PAS and PDS are modeled as a sum of Laplacian functions and exponential decaying functions, respectively     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

无线Mesh网络时延分析模型

无线Mesh网络由于拓扑结构、Mac协议、路由协议以及信道分配策略的复杂多变,其系统平均时延分析一直没有得到很好的解决。提出了一种基于排队论的时延分析模型,分析了在任意拓扑结构和路由协议下,处于基础工作模式的无线Mesh网络平均时延,并同时考虑了多收发器、多信道的影响。计算机仿真结果表明该模型能够比较准确的估计出网络性能,可以为无线Mesh网络部署以及优化提供理论依据。     

Adaptive sidelobe cancellation of wide-band multipath interference

The steady-state performance of a narrow-band sidelobe canceller using a single auxiliary element with tapped delay line is analyzed for a simple two-path interference model, and an impulse response model is developed to provide insight as to the cancellation performance that might be expected. Computer solutions are then presented for various combinations of signal and multipath parameters. It is shown that auxiliary delay taps are required for effective cancellation of wide-band multipath interference, even for fractional bandwidth-delay products. Good cancellation is generally achieved provided that 1) the delay line taps are spaced much closer than the Nyquist sampling rate, and 2) the total length of the delay line considerably exceeds the longest multipath delay, depending on multipath component strengths.     

Multipath propagation model of spatio-temporal dispersion observed at base station in urban areas

This paper presents a multipath propagation model for microcells in urban areas. The proposed model is a statistical geometric model that describes the propagation characteristics for propagation loss, power delay profiles, and power azimuth spectra. The applicable target of the proposed model is long-term characteristics such as the characteristics that depend on the height of a base station (BS) and the distance between the BS and a mobile station. Calculated power delay profiles and power azimuth spectra based on the model are similar to those of the power function. In order to verify the validity of the model, the power delay profiles and power azimuth spectra are measured. The measurement results agree well with the simulation results based on the model and the validity of the model is confirmed.     

基于路径时延模型的车联网数据分发方案

针对车联网的容迟特性造成通信资源受限的问题,提出了满足副本抑制要求的数据分发方案.方案利用马尔可夫链,通过交通网络的车辆概率分布建立路段的期望传输时延,并结合车辆的轨迹与目标位置的匹配度确定车辆的转发优先级.车辆为转发的每个数据包插入转发参数字段并通过同步反馈机制确定最终的转发车辆,确保由优先级最高的车辆完成转发.考虑到链路的稳定性,还推导了当前丢包率前提下,车辆接收数据包与发送次数之比,避免不必要的发送尝试产生大量副本.实验结果显示,提出的方案与基于轨迹预测的算法相比,有效提高了网络吞吐量和时延性能.