基站工程设备及网络测试的实践

本文以LTE基站工程配套设备单项工程(桂林)和4G网络一期工程基站主设备工程(桂林)基站设备安装及调测施工、验收为工程背景,简要探讨了移动通信基站设备及网络的测试等相关内容,仅供交流.     

基于双协议栈的IPv6网络性能测试系统的实现

IPv6网络性能测试是IPv6测试中的一个重要部分。针对目前IPv6网络性能测试软件的缺乏,在研究IPv6网络性能测试的性能指标、测试方法及测试结构的基础上,设计实现了一个W indows平台下IPv6网络性能测试系统IPv6PTS,并使用该系统实测了一个IPv6实验网的性能指标。实验表明,该系统具有较好的可扩展性和实用性。     

智能变电站系统网络性能测试与分析

网络是智能变电站信息交互的枢纽,信息传输实时性是否能满足变电站的要求是智能变电站的关键。本文结合某智能变电站系统网络性能测试的实际情况,分析了数据传输时延产生的原因。针对该问题,提出了基于优先级标签的变电站过程层(SESPL)信息综合传输方法,并对该方法有效性进行了验证。     

网络互联及常用互联设备应用详述

网络互联是构成计算机网络的最基本技术。文章介绍了网络互联的目的和所要解决的问题,并对实现网络互联的常用设备进行了较为详实的分析与比较。     

以太网控制器的嵌入式设备网络互连

RTL8019AS以太网（Ethernet）控制器在电子设备日趋网络化的背景下,被广泛应用于各种嵌入式设备上。本介绍以及网控制器RTL8019AS的结构;结合MOTOROLA的嵌入式MPUMC68VZ328,分析RTL8019AS的硬件和软件的设计。     

如何通过性能测试选购网络视频服务器

目前，市场上的网络视频服务器琳琅满目，面对如此众多的产品，用户该如何去选择？本文作者以其个人对视频服务器性能测试上的经验与读者进行分享，相信能有所助益。[编者按]     

基于节点和设备的网络测试

根据网络测试的方法,对动力部能调中心的网络进行节点和设备的网络测试,以确保网络畅通,性能稳定。     

局域网性能测试及研究

对网络性能的要求越来越高，对网络性能进行测试也就引起越来越多的关注。讨论了对局域网进行性能测试所需要的一些技术、参数、疗法及如何利用Java的网络功能编写测试程序，给出了测试方法，并对结果进行了分析。     

用多智能代理和网络数据流测试应用软件性能

现代信息系统中新型软件架构层出不穷,软硬件和网络通讯之间的相互关联作用日益复杂,加大了系统性能瓶颈查找的难度。文章探讨如何通过多智能代理技术等方法,截取、分析和回放网络数据流来评价软件系统的性能。     

无缓冲光互连网络的延时性能分析及优化

针对当前高性能计算机光互连网络中光缓冲不易实现的问题,提出一种无缓冲的光互连网络结构BOIN,在对网络结构进行建模和分析的基础上,研究网络的传输延时随不同输入负载和网络规模而变化的规律,给出在一定互连总规模和输入负载下,网络延时达到最小值时网络拓扑结构所必须满足的条件。模拟实验证明了该结果的正确性。     

卫星网络TCP/IP传输性能增强技术实验

本文在对卫星IP网络传输性能改善方法进行的简要介绍基础上,重点讨论了基于卫星关口站采用TCP存储、TCP欺骗等方法下对卫星IP网络性能的改善效果的实验。实验内容包括:1)不采用改善技术;2)只采用TCP存储技术;3)只采用TCP欺骗技术;4)同时采用存储和欺骗;5)地面系统五种条件下不同典型网站的接续时间和业务吞吐量的测量。实验结果显示,针对不同TCP数据类型,不同的改善方法的效果有所差异。通过本实验的结果和结论,能够为卫星传输TCP/IP数据技术的研究提供进一步的参考依据。     

基于RapidIO和存储映射的高速互连网络

分析当前高速互连网络中同时存在的TCP/IP, GAMMA, InfiniBand, SCI等技术的实现机制,介绍RapidIO高性能总线技术。研究RapidIO协议和MPC8548处理器的相关技术,提出在RapidIO高速互连网络中实现存储映射的通信技术解决方案。     

A Scalable Interconnection Network Architecture for Petaflops Computing

Extrapolating technology advances in the near future, a computer architecture capable of petaflops performance will likely be based on a collection of processing nodes interconnected by a high-performance network. One possible organization would consist of thousands of inexpensive, low-power symmetric multiprocessor (SMP) nodes. Each node will inject data into the interconnection network at a very large rate and consequently, the interconnect scheme is one of the most crucial design issues affecting system performance. This paper describes the 2D simultaneous optical multiprocessor exchange bus (2D SOME-Bus) which has the potential to become the basis of a high-end computer architecture capable of petaflops performance. It consists of N horizontal, N vertical 1D SOME-Bus networks, and N ² nodes. Each node is connected to one horizontal and one vertical 1D SOME-Bus. Each of N nodes connected to one 1D SOME-Bus has a dedicated broadcast channel and an input channel interface based on an array of N receivers monitoring all N channels and allowing multiple simultaneous broadcasts. In the 2D SOME-Bus, messages being broadcast on one Bus can be broadcast in a cut-through manner on one or more Buses in the other dimension. This paper describes the optoelectronic devices and technology which make the 2D SOME-Bus possible, and the network interface organization. It also presents simulation results which compare the performance of the 2D SOME-Bus, the 1D SOME-Bus, the crossbar and the torus under the message-passing paradigm.     

高速公路计算机网络性能检测

利用网络测试工具对高速公路计算机网络进行检测,快速发现网络设备存在的问题和整个网络系统的性能分析。     

A High-Performance and Cost-Efficient Interconnection Network for High-Density Servers

The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.     

神经网络软测量技术在通风机性能测试中的应用

将神经网络与软测量技术相结合,建立了通风机性能神经网络模型,并用测试数据进行了训练。结果表明,该方法是分析通风机性能的一种有效途径。     

新型互连网络NIN研究

以通信延迟和网络吞吐率这两个重要参数为出发点,以大规模并行处理系统的新型互连网络（ＮＩＮ）进行了理论分析和模拟测试,并与二维网格、环形网以及反图拓扑互连网络进行了比较,结果表明：与其它三种网络相比,ＮＩＮ不仅保持了反图拓扑互连网络可以连接更多处理机的优点,同时还具有较短的通信延迟和较高的网络吞吐率。