基于伪布尔可满足性的纳米CMOS电路单元配置

针对传统布尔可满足性(SAT)法在处理纳米CMOS电路(CMOL)单元配置时,存在合取范式(CNF)表示的约束子句个数过多、中间处理文件过大的问题,该文提出了利用伪布尔可满足性(PBS)来解决CMOL电路的单元配置问题。实验结果显示,相对于传统的SAT法,PBS法在不增加额外的布尔变量集个数的条件下,通过降低编码过程中的约束个数,能有效减少中间处理文件大小,达到提高算法效率和提高处理大电路的能力。     

Efficient logic architectures for CMOL nanoelectronic circuits

CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. Two new CMOL building blocks using transmission gates have been introduced to obtain efficient combinational and sequential logic for CMOL designs. Compared with the existing CMOL circuits, the proposed CMOL designs based on these blocks can achieve more than 30% improvement in speed and up to 80% improvement in density and power consumption while providing similar fault tolerance capabilities. This work significantly advances the applications of CMOL to actual electronic circuits and systems     

Three-dimensional CMOL: three-dimensional integration of CMOS/nanomaterial hybrid digital circuits

The CMOS molecular (CMOL) circuit is a promising hybrid structure incorporating the nanowire crossbar into the CMOS integrated circuit (IC) implementation. In this letter, a novel three-dimensional (3D) architecture of the CMOL circuit is introduced. This structure eliminates the special pin requirement of the original CMOL designs, providing a feasible and efficient solution to build the practical CMOL circuits. In this 3D structure, the density of the nanowire crossbar is doubled. Such a high-density implementation enables the 3D CMOL technology to leap ahead of the IC roadmap by more than three generations.     

CMOL: Second life for silicon?

This is a brief review of the recent work on the prospective hybrid CMOS/nanowire/nanodevice (“CMOL”) circuits including digital memories, reconfigurable Boolean-logic circuits, and mixed-signal neuromorphic networks. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with the extremely high potential density of molecular-scale two-terminal nanodevices. Relatively large critical dimensions of CMOS components and the “bottom-up” approach to nanodevice fabrication may keep CMOL fabrication costs at affordable level. At the same time, the density of active devices in CMOL circuits may be as high as 10¹² cm² and that they may provide an unparalleled information processing performance, up to 10²⁰ operations per cm² per second, at manageable power consumption.     

Spotlight on memory: an optically biased, single-ended, three transistor, fully static RAM cell

A single-ended static memory scheme combining advantages of both a one-transistor dynamic RAM (DRAM) cell and a six-transistor static RAM (SRAM) cell is proposed in this article. For the first time, optical bias is introduced, converting the classical complementary metal-oxide semiconductor (CMOS) RAM to an optoelectronic device. The cell structure is highly scalable and cost effective. Various approaches and schemes were applied to combine advantages of static and dynamic RAM memories, striving to shorten access times, lower power dissipation, and decrease cell area. This is particularly true for system-on-a-chip (SoC) and embedded memories. Here, the novel approach towards the same goal is proposed and simulated, introducing standard CMOS technology. A single-ended, three-transistor, fully static RAM cell is demonstrated.     

A novel memory cell for multiport RAM on 0.5 μm CMOSSea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V     

Cortical Models Onto CMOL and CMOS— Architectures and Performance/Price

Here we introduce a highly simplified model of the neocortex based on spiking neurons, and then investigate various mappings of this model to the CMOL CrossNet nanogrid nanoarchitecture. The performance/price is estimated for several architectural configurations both with and without nanoscale circuits. In this analysis we explore the time multiplexing of computational hardware for a pulse-based variation of the model. Our analysis demonstrates that the mixed-signal CMOL implementation has the best performance/price in both nonspiking and spiking neural models. However, these circuits also have serious power density issues when interfacing the nanowire crossbars to analog CMOS circuits. Although the results presented here are based on biologically based computation, the use of pulse-based data representation for nanoscale circuits has much potential as a general architectural technique for a range of nanocircuit implementation.     

Basic operation of novel ferroelectric CMOS circuits

A nonvolatile ferroelectric complementary metal-oxide-semiconductor (CMOS) circuit with both logic and memory functions is proposed as a new application of ferroelectric field effect transistors. The logic and memory operations of a NOT-logic ferroelectric CMOS device is demonstrated. Nondestructive readings of high and low output voltage levels of the device were performed. Data retention was measured up to 10⁵ s (1.2 days).     

A novel pseudo-floating-gate flash EEPROM device (Ψ-cell)

The purpose of this paper is to present a novel Pseudo-Floating-Gate Flash EEPROM cell which has certain advantages over the classical structure and, therefore, it seems adequate for multi-MBit memory arrays as well as for CMOS embedded memory applications. The proposed cell is based on the series resistance modification concept and exhibits the following characteristics: 1) simplicity, 2) dimensions as small as a MOSFET, 3) the ability to follow the shrink rate of CMOS devices, 4) the ability to be easily embedded in CMOS, 5) low-power compatibility, and 6) insensitivity to depletion phenomena. All these features make this device very attractive for future NVM applications     

可用于高密度高速度领域的一种新型两端静态存储单元的设计

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLS1 applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability.     

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.     

小容量相变存储器芯片版图设计与验证分析

设计了基于1T1R结构的16 kb相变存储器(PCRAM)芯片及其版图。芯片包括存储阵列、外围读写控制电路、纠错电路(ECC)、静电防护电路(ESD)。版图上对纳米存储单元(1R)与CMOS工艺的融合作了优化处理,给出了提高存储单元操作电流热效率的具体方法。1R位于顶层金属(TM)和二层金属(TM-1)之间,包含存储材料以及上下电极,需要在传统CMOS工艺基础上添加掩膜版。读出放大器采用全对称的差分拓扑结构,大大提升了抗干扰能力、灵敏精度以及读出速度。针对模块布局、电源分配、二级效应等问题,给出了版图解决方案。采用中芯国际130 nm CMOS工艺流片,测试结果显示芯片成品率(bit yield)可达99.7%。     

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

With a great scalability potential, nonvolatile magnetoresistive memory with spin-torque transfer (STT) programming has become a topic of great current interest. This paper addresses cell structure design for STT magnetoresistive RAM, content addressable memory (CAM) and ternary CAM (TCAM). We propose a new RAM cell structure design that can realize high speed and reliable sensing operations in the presence of relatively poor magnetoresistive ratio, while maintaining low sensing current through magnetic tunneling junctions (MTJs). We further apply the same basic design principle to develop new cell structures for nonvolatile CAM, and TCAM. The effectiveness of the proposed RAM, CAM and TCAM cell structures has been demonstrated by circuit simulation at 0.18 $ mu$m CMOS technology.      

A novel fully CMOS process compatible PREM for SOC applications

A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.     

High-density CMOS ROM arrays

A single transistor cell and a precharge signal are used to reduce the memory cell area in bulk CMOS ROM arrays to 1.12 mil/SUP 2//bit. Use of SOS/CMOS technology further reduces the memory cell area to 0.38 mil/SUP 2//bit and makes possible CMOS ROMs of up to 32768 bits. Operation of both the array and the decoders is controlled by a precharge signal which is generated internally in a way which is transparent to the user. The CMOS ROMs thus produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl deg/C temperature range.     

A DOL CMOS static memory cell

A new CMOS static memory cell, called the double-lambda diode (DOL), is described. It offers the speed and the power dissipation advantages of conventional CMOS static memory cells at half the area. The cell uses complementary depletion MOS devices. The processing technology is based on a twin-tub CMOS process. Using 2.5 /spl mu/m design rules the cell area is 500 /spl mu/m/SUP 2/. In addition, a 300 /spl mu/m/SUP 2/ single-lambda diode (SIL) cell using a poly resistor as a load is discussed. Comparisons of these cells with other MOS static memory cells are presented.     

13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

The development is discussed for a 13-ns, 500-mW, 16K word/spl times/4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS) technology that combines a bipolar and a CMOS device on the same chip. The power dissipation of the RAM is about one half that of the conventional 64-kb bipolar ECL RAM. This high-speed, low-power RAM has been realized through a concept of a MOS-type memory cell, bipolar circuits, and a CMOS combination gate to allow for increased LSI integration.     

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking

This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. In line-based QCA memory cells, data bits are stored oscillating along QCA lines. The best known line-based memory cell implementation requires three new clocking zones in addition to the four clocking zones defined by the conventional QCA clocking scheme and utilizes three parallel clocking zones per cell. The proposed memory cell requires only two new clocking zones and utilizes two parallel clock zones per memory cell; permitting less CMOS circuity for clock design and denser QCA system implementations. Furthermore, read throughput is improved to one operation per clock cycle (from one read per two clock cycles). Simulations with the $hbox{tt QCADesigner}$ simulator are performed to verify the functionality of the proposed QCA memory cell.      

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET²RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility