A monolithic 14 bit A/D converter

A 14 bit monolithic successive approximation A/D converter with 7 /spl mu/s conversion time is described. A special system called `dynamic element matching' is used to construct the high-accuracy D/A converter needed in the system. The high linearity of the converter (/spl plusmn//SUP 1///SUB 4/ LSB) results in an 84 dB S/N ratio. The high-speed comparator consists of a wide-band (75 MHz) clamped operational amplifier followed by a strobed flip-flop to freeze the output data. In the digital part, current mode logic (CML) is used for speed and low interference generation with respect to the analog circuitry. Digital input and outputs are TTL compatible. A low-noise, high-stability reference source with a temperature dependence of /spl plusmn/0.5 ppm//spl deg/C over -20 to +85/spl deg/C completes the A/D function. The chip is processed in a standard bipolar process using double layer interconnection. The die size is 3.5/spl times/4.4 mm/SUP 2/.     

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.     

Second generation I/SUP 2/L/MTL: a 20 ns process/structure

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.     

A fully parallel 10-bit A/D converter with video speed

Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a parallel converter leads to a high number of components and large power dissipation. Therefore, a circuit with a reduced number of components and optimized power has been used. The process employed is a 3 /spl mu/m bipolar process, which integrates about 40000 elements onto a 9.2/spl times/9.8 mm chip.     

A monolithic 14-bit D/A converter

A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.     

A low-pass biquad derived filter realization

A biquad derived structure employing two Norton (current differencing) amplifiers is presented which requires the minimum number of components. Transfer characteristics of the form K/SUB 1//D(S) and K/SUB 2/(S+/spl omega//SUB n//Q)/D(S) with D(S)=S/SUP 2/+/spl omega//SUB n/S/Q+/spl omega//SUB n//SUP 2/ are realized. Biasing constraints are of major importance in the detailed realization and a typical circuit design is presented along with a discussion of its performance, which is compared with that of others.     

Comments on `Silicon MESFET digital circuit techniques'

See also ibid., vol.SC-16, p.578-84 (Oct. 1981). It is shown that the design criterion for MESFET ED logic assumed by Hartgring et al.-that the low voltage level must be less than /SUP 1///SUB 3/ V/SUB T/-is overly restrictive, and that the technology is more tolerant of V/SUB T/ variation than would be surmised from such an assumption. Data for the operation of a MESFET ED logic divide-by-four circuit over a temperature range from 25/spl deg/C to 145/spl deg/C confirms the wider operating margin of this technology.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

Monolithic analog multiplier-divider

The design of a precision general-purpose monolithic analog multiplier-divider based on the principle of the variable transconductance of bipolar transistors is described. The device has two new aspects: first, an eight-transistor multiplier-divider core, and second, an improvement in the accuracy and high-frequency behavior of the input and output circuits having monolithic conversion resistors. The transfer function /spl nu//SUB w/=/spl nu//SUB x//spl nu//SUB y///spl nu//SUB z/ is only dependent on external voltages. An advantage of the multiplier-divider over a multiplier with a fixed internal voltage reference is that the external signal voltages can be accurately related to the relevant reference voltage. Moreover, the additional divider input enlarges the application field. The maximum signal voltages are /spl plusmn/10 V. The untrimmed inaccuracy is typically 2 percent. The nonlinearity is /spl plusmn/0.1 percent. The bandwidth is 6.5 MHz, and the slew rate is 50 V//spl mu/s.     

A monolithic high-power series voltage regulator

A complete series voltage regulator circuit capable of delivering /SUP 1///SUB 2/ ampere of current has been built on a single 63/spl times/66-mil die using the conventional all- diffused processing technology. Improved performance has been achieved by using an internal low-power voltage regulator to supply the desired dc output voltage reference directly to a second main regulator. This permits the dc and ac characteristics of the regulator to be separately optimized with the result that excellent transient characteristics are realized simultaneously with low drift and excellent regulation.     

A fast, latching comparator for 12 bit A/D applications

High-speed, 12 bit accurate successive approximation A/D converters demand a comparator with both excellent input specifications and fast response time. The author describes a voltage comparator with 50 ns response time to 1/2 LSB overdrive (1.2 mV) and 0.1 LSB (250 /spl mu/V) total input error. Unique features of the circuit include a super-/spl beta/ input stage, a fast buried-zener level-shift, a fully differential output stage, a floating-zener biasing scheme, and a fast latch circuit which does not interfere with input accuracy. The comparator is manufactured on a bipolar, double-implanted, thin epi, junction-isolated process.     

Logic gates with shaped Josephson junctions

Long (L//spl lambda//SUB j/>5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (/spl lambda//SUB j/ being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed sidelobes, providing good logic gain and permitting logic fan-in with multiple control lines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I/SUB G//spl sime/6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3/spl times/10/SUP -15/ J.     

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.     

An isolated vertical n-p-n transistor in an n-well CMOS process

Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source and drain implant dose and an increase in the final anneal time, but no extra processing steps of masks were required. The n-p-n transistors had generally good characteristics, with H/SUB FE//spl ap/600 and BV/SUB CEO//spl ap/40 V, while the MOS characteristics were unchanged.     

A micropower, small input-to-output delay, high-voltage bipolar driver/demultiplexer IC

Describes a 2.6/spl times/2.6 mm bipolar driver/demultiplexer integrated circuit used to selectively switch one of six off-chip MOS devices. A carefully chosen chip architecture coupled with novel circuit techniques has reduced power consumption by more than two orders of magnitude over currently available micropower drivers that offer comparable performance. A low-voltage bipolar process (BV/SUB CEO/>20 V) that utilizes an extra deep n/SUP +/ diffusion (d-n/SUP +/) combines I/SUP 2/L and linear circuitry to achieve a micropower function (<100 /spl mu/W) with small input-to-output delay (<400 ns) and high-voltage capability (40 V max).     

An efficient CMOS buffer for driving large capacitive loads

A CMOS class AB high-drive buffer suitable for driving large capacitive and moderate resistive loads is presented. The buffer, designed using 3-/spl mu/m technology, occupies only 100 mils/SUP 2/ of area and dissipates 1.5 mW of DC power from a /spl plusmn/2.5-V supply, yet it is capable of driving a 5000-pF capacitor at over 100-kHz clocking frequency. The buffer achieves good slew rate and fast settling by entering into a high-drive state during slewing and returning to a low-power wide-band state during the settling period. Unconditional stability is attained when C/SUB L//spl ges/100 pF and R/SUB L//spl ges/10 k/spl Omega/. Total harmonic distortion is below 0.5% for over 70% of the full supply range.     

High-resolution A/D conversion in MOS/LSI

A new successive approximation analog-to-digital conversion technique compatible with most MOS process technologies is described. This technique combines a string of equal value diffused resistors and a binary ratioed capacitor array in a unique circuit configuration so that 12-bit monotonicity is achieved with only 8-bit ratio-accurate circuit elements. The comparator is realized by a chopper-stabilized amplifier to reduce the inherently high input offset voltages of MOS amplifiers. Typical performance characteristics taken from a sample of ICs are presented; 12-bit monotonic conversion with differential nonlinearity less than 1/2 LSB is completed in 50 /spl mu/s. The die area, less logic, is 12000 mil/SUP 2/. Because of assured 12-bit monotonicity, this converter should find applications of closed-loop control systems. It seems feasible to extend this technique to 14-bit resolution for use in applications such as digital audio systems.     

A high-frequency temperature-stable monolithic VCO

A new high-frequency monolithic voltage-controlled oscillator (VCO) is described that achieves /spl plusmn/60 ppm//spl deg/C temperature coefficient of frequency over 0-75/spl deg/C at center frequencies from DC to 20 MHz. The circuit also exhibits good linearity of voltage to frequency, and excellent triangle output waveform over the whole frequency range from low frequencies to 20 MHz. The circuit is fabricated using an eight mask IC process and has a die size of 65/spl times/50 mils/SUP 2/.     

I/SUP 2/L current gain design

A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.     

Stable voltage reference sources

A family of well-regulated voltage references are shown, which are readily integrable for use with emitter-coupled logic, threshold logic, or linear circuit arrays. By relying on the relatively well-matched characteristics and the temperature tracking of integrated transistors and resistor ratios, the circuit can provide a large range of output fractions of the power supply. The relationships of the circuit components for various output voltages are derived. One circuit configuration gives fractions of the power supply of less than /SUP 1///SUB 2/ while another configuration gives fractions of the power supply greater than /SUP 1///SUB 2/. Limitations of the obtainable fractions are given. Experimental results are shown for each of the two basic circuit configurations and the temperature stability is demonstrated. Well-defined stable voltages are thus derived with a minimum of components and power drain.