PCB设计中同步开关噪声问题分析

印刷电路板设计中的同步开关噪声问题是现代高速数字电路应用的瓶颈之一。介绍了一 种在电路板上施加同步开关报文和温度应力的可靠性测试方法,该方法可以有效暴露电路 板上的同步开关噪声问题。借助噪声测试和阻抗分析手段,对一个由该方法发现的异常问 题进行了分析,通过优化去耦电容和电源平面阻抗,抑制了电路板上的同步开关噪声, 问题得到了完美解决。最后,给出了一些在PCB设计中抑制同步开关噪声的方法和建议。     

减小CMOS电路同步开关噪声的设计方法探讨

随着集成电路的快速发展，同步开关噪声对系统电学性能的影响越来越大。本文介绍了一种减少同步开关噪声的设计方法，即基于对同步开关噪声简化模型的分析，采取先去除直通电流再降低输出级的电压变化率方法减小同步开关噪声，并通过时序控制逻辑电路和可控电压变化率电路来实现。     

一种基于0.18μm的同步开关输出噪声模型和仿真方法

0．18μm下,同步开关输出噪声是影响信号完整性的主要噪声之一,较大的噪声有可能导致数字系统中元件的误动。本文首先简要介绍了同步开关输出噪声的产生和特点,然后给出了一种建立仿真模型和仿真的方法,这种方法快速简便而且结果精确。最后根据仿真的结果得到了一些减小同步开关输出噪声的方案。     

多层封装基板中同步开关噪声研究

文章以栅格阵列封装(land grid array,LGA)模型为研究对象,分析了多层封装基板中的同步开关噪声(simultaneous switching noise,SSN)问题。首先利用频域仿真工具PowerSI得到了键合线和信号布线的S参数模型。然后通过在电路仿真工具HSPICE中加载封装结构的S参数模型和驱动器模型来仿真同步开关噪声。最后在设计中选取在多层基板上添加去耦电容的方式来减小同步开关噪声。仿真结果表明,通过在本LGA多层基板设计中添加110pF容值的去耦电容,可以较好地减少同步开关噪声,满足设计要求。     

用于减小同步开关噪声的OCD输出驱动电路的设计

分析了同步开关噪声产生的机理,从电路设计技术角度讨论了输出驱动器电路的设计方法,提出了一种用于改善输出驱动电路同步开关噪声性能的OCD输出驱动电路的设计,并给出了实际的OCD电路。     

用于减小同步开关嗓声的OCD输出驱动电路的设计

分析了同步开关噪声产生的机理,从电路设计技术角度讨论了输出驱动器电路的设计方法,提出了一种用于改善输出驱动电路同步开关噪声性能的ＯＣＤ输出驱动电路的设计,并给出了实际的ＯＣＤ电路。     

一种基于频率同步的低噪声电源适配器设计

针对电源适配器高频开关信号的噪声干扰对某些精密仪器性能(如B超机显示清晰度)的影响问题,本文提出通过适配器开关频率和系统设备工作频率同步方式解决噪声干扰的设计思路,以便携式B超机电源适配器设计实践为例,介绍了同步电路的设计方法、功率电路拓扑和辅助电源方案;同步功能通过实验验证,采用该方案的电源适配器已成功应用于某全球知名B超机产品。     

基本电子电路

f洲了多芯片胡.件中带裂缝电源/接地板同步开关噪声分析/帆(上海交通大学){{上海交大学报.一2002,36(12)2003020819王德东,李征 一1785-1787电源接地板上的同步开关噪声是制约高速电路发展的瓶颈,而目前同步开关噪声分析集中于规则电源接地板,与实际电路有一定差距.文中基于部分等效元方法分析多芯片组件中带裂缝的电源/接地板上的同步开关噪声;对不同尺寸位置的裂缝引起的同步开关噪声进行相应的时域模拟,得出了多芯片组件中电源/接地板上裂缝对同步开关噪声的影响.图6参6(木)TN711 2003020820模拟开关电路潜在电路分析软件算法的研究/马…     

PEEC结合有理缩减技术分析高速集成电路中同步开关噪声

利用部分元件等效电路 ( PEEC)方法分析高速集成电路系统中同步开关噪声 ,该方法相比其它等效电路方法及全波分析方法 ,具有简单、效率高 ,并可以和无源电路阶数缩减方法结合 ,进行大规模缩减 ,从而进一步提高计算速度。通过对电路中两种典型结构体 (电源 /接地板 ,电源板 /信号线 /接地板 )上同步开关噪声的分析 ,表明这种方法是分析高速集成电路中同步开关噪声的高效方法。     

电磁带隙结构在同步开关噪声抑制中的应用分析

随着数字电路的噪声容限和时序容限不断减小,电源地平面上的同步开关噪声(SSN)成为高速设计的主要瓶颈之一.而现有抑制SSN的方法存在各自的不足,因而提出采用电磁带隙结构(EBG)设计来抑制SSN,软件仿真证明该方法是有效的.基于对多种不同结构EBG的研究,给出了EBG的设计思路和最新发展趋势,为今后的实际应用研究提供一定的参考与指导.     

基于宏模型的同步开关噪声仿真分析

同步开关噪声(SSN)对具有上百个输入/输出端口的高性能FPGA系统具有很大的影响,已经成为深亚微米设计所必须考虑的主要问题之一.由于没有考虑电压反馈效应,IBIS模型在仿真SSN时,总是过高估计电源噪声、地噪声和静线噪声.为提高IBIS模型仿真SSN的精度提出了一种改进的方法,利用自研发的工具SSWI(SSN simulation with IBIS)获得了自动IBIS优化模型.利用美国北卡州立大学开发的工具S2IBIS直接从SPICE模型中提取了IBIS模型,与SPICE模型仿真结果验证了该方法的有效性,采用该法可以提高IBIS模型仿真SSN的精度60%～70%.     

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.     

A Double-Surface Electromagnetic Bandgap Structure With One Surface Embedded in Power Plane for Ultra-Wideband SSN Suppression

In this letter, a double-surface electromagnetic bandgap (EBG) structure with one EBG surface embedded in power plane is proposed for ultra-wideband simultaneous switching noise (SSN) suppression in printed circuit boards. The SSN suppression bandwidth is broadened to wider than 30 GHz with a low start frequency by combining traditional EBG structure and the coplanar EBG structure which is embedded in the power plane. Because the coplanar EBG surface is embedded in the power plane, no additional metal layer is introduced by the double-surface EBG structure. Simulations and measurements are performed to verify the broadband SSN suppression, high performance is observed.     

Modeling of simultaneous switching noise in high speed systems

Simultaneous switching noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex: due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition theory. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a test vehicle, verifying the validity of the method. In addition a system has been simulated to compute SSN, showing the application of this method for complex systems     

Bandwidth Enhancement for SSN Suppression Using a Spiral‐Shaped Power Island and a Modified EBG Structure for a λ/4 Open Stub

This paper proposes a spiral‐shaped power island structure that can effectively suppress simultaneous switching noise (SSN) when the power plane drives high‐speed integrated circuits in a small area. In addition, a new technique is presented which greatly improves the resonance peaks in a stopband by utilizing λ/4 open stubs on a conventional periodic electromagnetic bandgap (EBG) power plane. Both proposed structures are simulated numerically and experimentally verified using commercially available 3D electromagnetic field simulation software. The results demonstrate that they achieve better SSN suppression performance than conventional periodic EBG structures.     

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach.     

A simple finite-difference frequency-domain (FDFD) algorithm for analysis of switching noise in printed circuit boards and packages

Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). Several methods have been used to investigate SSN. These methods ranged from simple lumped circuit models to full-wave (dynamic) three-dimensional Maxwell equations simulators. In this work, we present an efficient and simple finite-difference frequency-domain (FDFD) based algorithm that can simulate, with high accuracy, the capacity of a PCB board to introduce SSN. The FDFD code developed here also allows for simulation of real-world decoupling capacitors that are typically used to mitigate SSN effects at sub 1 GHz frequencies. Furthermore, the algorithm is capable of including lumped circuit elements having user-specified complex impedance. Numerical results are presented for several test boards and packages, with and without decoupling capacitors. Validation of the FDFD code is demonstrated through comparison with other algorithms and laboratory measurements.     

Design and modeling of high-impedance electromagnetic surfaces for switching noise suppression in power planes

This paper presents a detailed design and modeling approach for power planes with integrated high-impedance electromagnetic surfaces (HIS). These novel power planes, which were introduced recently, have the unique ability of providing effective broadband simultaneous switching noise (SSN) mitigation. Full-wave electromagnetic simulation is used to study the impact of the geometry on the performance of these novel power planes. It is demonstrated that power planes using inductance-enhanced HIS can be designed for broadband mitigation of the SSN from the upper hundred megahertz to the gigahertz frequencies. Physics-based compact models for the unit cell of power planes with integrated HIS are developed and several of them connected in a two-dimensional array to build full models for large and multilayer power planes. The compact model offers fast analysis of power planes. As an example, we show that the full-wave simulation time of a 10/spl times/10 cm power plane with integrated HIS can be dramatically reduced from 24 to 48 h using a commercially available three-dimensional full-wave solver to less than 1 min when using the compact circuit model developed here.