Remote p-doping of InAs nanowires

We report on remote p-type doping of InAs nanowires by a p-doped InP shell grown epitaxially on the core nanowire. This approach addresses the challenge of obtaining quantitative control of doping levels in nanowires grown by the vapor-liquid-solid (VLS) mechanism. Remote doping of III-V nanowires is demonstrated here with the InAs/InP system. It is especially challenging to make p-type InAs wires because of Fermi level pinning around 0.1 eV above the conduction band. We demonstrate that shielding with a p-doped InP shell compensates for the built-in potential and donates free holes to the InAs core. Moreover, the off-current in field-effect devices can be reduced up to 6 orders of magnitude. The effect of shielding critically depends on the thickness of the InP capping layer and the dopant concentration in the shell.     

Purification of cadmium up to 5N+ by vacuum distillation

Cadmium was refined by vacuum distillation, a technique suitable for low boiling and melting point materials, to remove the heavy and low vapour pressure impurities at ppm level. The detailed analysis of the purified Cd as well as raw Cd was done by ICP-OES techniques for 27 impurity elements. Purification was carried out in an efficient high-yield vacuum distillation system designed and fabricated for purifying 3N+ purity indigenous cadmium to 5N+ (99.999%). Analysis confirmed the reduction of total impurity content from 134 ppm (3N7) for raw Cd to 3 ppm (5N7) upon vacuum distilled Cd. The present study shows that the analysis of impurities such as Fe, Mg and Ca are contributed from environmental effect, whereas impurities such as Pb, Bi, Ag, Ni, Cu, Zn and Tl require adaptation of elemental analysing technique to counter dilution effect. The Hg trace analysis can however be carried out by hydride generation techniques.     

Confinement and surface effects in B and P doping of silicon nanowires

Several experimental groups have achieved effective n- and p-type doping of silicon nanowires (SiNWs). However, theoretical analyses on ultrathin SiNWs suggest that dopants tend to segregate to their surfaces, where they would combine with defects such as dangling bonds (DB), becoming electronically inactive. Using fully ab initio calculations, we show that the differences in formation energies among surface and core substitutional sites decrease rapidly as the diameters of the wires increase, indicating that the dopants will be uniformly distributed. Moreover, occurrence of the electronically inactive impurity/DB complex rapidly becomes less frequent for NWs of larger diameters. We also show that the high confinement in the ultrathin SiNWs causes the impurity levels to be deeper than in the silicon bulk, but our results indicate that for NWs of diameters larger than approximately 3 nm the impurity levels recover bulk characteristics. Finally, we show that different surfaces will lead to different dopant properties in the gap.     

Band-offset driven efficiency of the doping of SiGe core-shell nanowires

Impurity doping of semiconducting nanowires has been predicted to become increasingly inefficient as the wire diameter is reduced, because impurity states get deeper due to quantum and dielectric confinement. We show that efficient n- and p-type doping can be achieved in SiGe core-shell nanowires as thin as 2 nm, taking advantage of the band offset at the Si/Ge interface. A one-dimensional electron (hole) gas is created at the band-edge and the carrier density is uniquely controlled by the impurity concentration with no need of thermal activation. Additionally, SiGe core-shell nanowires provide naturally the separation between the different types of carriers, electron and holes, and are ideally suited for photovoltaic applications.     

Role of molecular surface passivation in electrical transport properties of InAs nanowires

The existence of large densities of surface states on InAs pins the surface Fermi level above the conduction band and also degrades the electron mobility in thin films and nanowires. Field effect transistors have been fabricated and characterized in the "as fabricated" state and after surface passivation with 1-octadecanethiol (ODT). Electrical characterization of the transistors shows that the subthreshold slope and electron mobility in devices passivated with ODT are superior to the respective values in unpassivated devices. An X-ray photoelectron spectroscopy study of ODT passivated undoped InAs nanowires indicates that sulfur from ODT is bonded to In on the InAs nanowires. Simulations using a two-dimensional device simulator (MEDICI) show that the improvements in device performance after ODT passivation can be quantified in terms of a decrease of interface trap electron donor states, shifts in fixed interfacial charge, and changes in body and surface mobilities.     

Polarization-induced pn diodes in wide-band-gap nanowires with ultraviolet electroluminescence

Almost all electronic devices utilize a pn junction formed by random doping of donor and acceptor impurity atoms. We developed a fundamentally new type of pn junction not formed by impurity-doping, but rather by grading the composition of a semiconductor nanowire resulting in alternating p and n conducting regions due to polarization charge. By linearly grading AlGaN nanowires from 0% to 100% and back to 0% Al, we show the formation of a polarization-induced pn junction even in the absence of any impurity doping. Since electrons and holes are injected from AlN barriers into quantum disk active regions, graded nanowires allow deep ultraviolet LEDs across the AlGaN band-gap range with electroluminescence observed from 3.4 to 5 eV. Polarization-induced p-type conductivity in nanowires is shown to be possible even without supplemental acceptor doping, demonstrating the advantage of polarization engineering in nanowires compared with planar films and providing a strategy for improving conductivity in wide-band-gap semiconductors. As polarization charge is uniform within each unit cell, polarization-induced conductivity without impurity doping provides a solution to the problem of conductivity uniformity in nanowires and nanoelectronics and opens a new field of polarization engineering in nanostructures that may be applied to other polar semiconductors.     

生长温度对InAs/GaAs横向异质结构纳米线形貌及晶体结构的影响

低维半导体材料因其超常的物理性能而受到了广泛关注和研究。本文采用金属有机物化学气相沉积（MOCVD）技术,利用金作催化剂制备了InAs/GaAs横向异质结构纳米线,并讨论了不同生长温度情况下InAs横向异质材料对纳米线形貌及晶体结构的影响。提高InAs材料的生长温度,可以有效地抑制纳米线的纵向生长,使其实现横向异质结构的生长。在异质结构纳米线横向生长时发生了侧面晶面旋转的现象,这是纳米线表面重构后侧面趋向能量更低的晶面的结果。本文的研究工作为推动微纳技术的发展提供了相应的理论基础和科学依据。      

真空蒸馏法从粗铟中脱除镉锌铊铅的研究

利用纯度为99.7%粗铟为原料,采用真空蒸馏的方法从粗铟中直接脱除镉、锌、铊、铅。分别进行了蒸馏温度、蒸馏时间、投料量等的条件实验。结果表明,控制真空度1~5 Pa,蒸馏温度950℃,蒸馏120 min,可将粗铟中镉、锌、铊、铅可除至6N高纯铟要求。并且以实验结果为依据计算出产物中各种杂质的挥发系数、分离系数、活度系数,对铟的热力学数据的完善有一定的参考意义。     

P型高阻CdZnTe晶体表面接触的电学性能研究

用原子力显微镜（ＡＦＭ）研究了Ｐ型高阻Ｃｄ０．８Ｚｎ０．２Ｔｅ晶体表面状况对接触电学特性的影响,研究了三种金属和ＡｕＣｌ３作为接触层材料的电学特性和接触机理。研究表明采用化学方法沉积ＡｕＣｌ３膜能在ＣｄＺｎＴｅ光滑表面形成一层重掺杂层,较金属更易获得欧姆接触,热处理可改善接触的欧姆性,增强接触层与晶体表面的结合力。     

Synthesis, contact printing, and device characterization of Ni-catalyzed, crystalline InAs nanowires

InAs nanowires have been actively explored as the channel material for high performance transistors owing to their high electron mobility and ease of ohmic metal contact formation. The catalytic growth of nonepitaxial InAs nanowires, however, has often relied on the use of Au colloids which is non-CMOS compatible. Here, we demonstrate the successful synthesis of crystalline InAs nanowires with high yield and tunable diameters by using Ni nanoparticles as the catalyst material on amorphous SiO2 substrates. The nanowires show superb electrical properties with field-effect electron mobility ~2700 cm2/Vs and ION/IOFF >103. The uniformity and purity of the grown InAs nanowires are further demonstrated by large-scale assembly of parallel arrays of nanowires on substrates via the contact printing process that enables high performance, “printable” transistors, capable of delivering 5 10 mA ON currents (~400 nanowires).     

Effect of annealing temperature on the characteristics and sensing properties of WO<Subscript>3</Subscript> nanowires

A uniform WO₃ nanowire structure was prepared by two-step thermal oxidation method on Si substrate. WO₃ nanowires show different morphology and crystal structures after annealing at different temperatures. The influence of annealing temperature on WO₃ nanowires was investigated by SEM, TEM and XRD. Higher crystallization property and lower surface state was obtained with higher annealing temperature. The gas sensing properties of the WO₃ nanowires with various annealing temperatures to NO₂ with the concentration ranging from 1 to 4 ppm were examined at different temperatures ranging from room temperature to 200 °C. The results indicate that WO₃ nanowires can greatly lower the working temperature of sensors and sensors based on WO₃ nanowires show p-type or n-type sensing behaviors depending on annealing temperatures. Possible sensing mechanism of p-type WO₃ nanowires and the influence of annealing temperature on sensing types was explained. This work might supply new ideas about gas sensing mechanisms and open a new way to develop p-type WO₃ sensing materials.     

Precursor evaluation for in situ InP nanowire doping

The use of tetraethyltin (TESn) and dimethylzinc (DMZn) as in situ n-?and p-dopant precursors during particle-assisted growth of InP nanowires is reported. Gate voltage dependent transport measurements demonstrate that the nanowires can be predictably synthesized as either n-?or p-type. These doped nanowires can be characterized based on their electric field response and we find that n-type doping scales over a range from 10(17) to 10(19)?cm(-3) with increasing input TESn dopant molar fraction. On the other hand, the p-type doping using DMZn saturates at low levels, probably related to a strong increase in nanowire growth rate with increasing DMZn molar fractions. By optimizing growth conditions with respect to tapering, axial pn-junctions exhibiting rectifying behavior were fabricated. The pn-junctions can be operated as light emitting diodes.     

Scanned probe imaging of quantum dots inside InAs nanowires

We show how a scanning probe microscope (SPM) can be used to image electron flow through InAs nanowires, elucidating the physics of nanowire devices on a local scale. A charged SPM tip is used as a movable gate. Images of nanowire conductance versus tip position spatially map the conductance of InAs nanowires at liquid-He temperatures. Plots of conductance versus backgate voltage without the tip present show complex patterns of Coulomb-blockade peaks. Images of nanowire conductance identify their source as multiple quantum dots formed by disorder along the nanowire--each dot is surrounded by a series of concentric rings corresponding to Coulomb blockade peaks. An SPM image locates the dots and provides information about their size. In this way, SPM images can be used to understand the features that control transport through nanowires. The nanowires were grown from metal catalyst particles and have diameters approximately 80 nm and lengths 2-3 microm.     

Inducing imperfections in germanium nanowires

Nanowires with inhomogeneous heterostructures such as polytypes and periodic twin boundaries are interesting due to their potential use as components for optical,electrical,and thermophysical applications.Additionally,the incorporation of metal impurities in semiconductor nanowires could substantially alter their electronic and optical properties.In this highlight article,we review our recent progress and understanding in the deliberate induction of imperfections,in terms of both twin boundaries and additional impurities in germanium nanowires for new/enhanced functionalities.The role of catalysts and catalyst-nanowire interfaces for the growth of engineered nanowires via a three-phase paradigm is explored.Three-phase bottom-up growth is a feasible way to incorporate and engineer imperfections such as crystal defects and impurities in semiconductor nanowires via catalyst and/or interfacial manipulation."Epitaxial defect transfer"process and catalyst-nanowire interfacial engineering are employed to induce twin defects parallel and perpendicular to the nanowire growth axis.By inducing and manipulating twin boundaries in the metal catalysts,twin formation and density are controlled in Ge nanowires.The formation of Ge polytypes is also observed in nanowires for the growth of highly dense lateral twin boundaries.Additionally,metal impurity in the form of Sn is injected and engineered via third-party metal catalysts resulting in above-equilibrium incorporation of Sn adatoms in Ge nanowires.Sn impurities are precipitated into Ge bi-layers during Ge nanowire growth,where the impurity Sn atoms become trapped with the deposition of successive layers,thus giving an extraordinary Sn content (＞6 at.％) in Ge nanowires.A larger amount of Sn impingement (＞9 at.％) is further encouraged by utilizing the eutectic solubility of Sn in Ge along with impurity trapping.     

Uniform and position-controlled InAs nanowires on 2" Si substrates for transistor applications

This study presents a novel approach for indirect integration of InAs nanowires on 2' Si substrates. We have investigated and developed epitaxial growth of InAs nanowires on 2' Si substrates via the introduction of a thin yet high-quality InAs epitaxial layer grown by metalorganic vapor phase epitaxy. We demonstrate well-aligned nanowire growth including precise position and diameter control across the full wafer using very thin epitaxial layers (<300 nm). Statistical analysis results performed on the grown nanowires across the 2' wafer size verifies our full control on the grown nanowire with 100% growth yield. From the crystallographic viewpoint, these InAs nanowires are predominantly of wurtzite structure. Furthermore, we show one possible device application of the aforementioned structure in vertical wrap-gated field-effect transistor geometry. The vertically aligned InAs nanowires are utilized as transistor channels and the InAs epitaxial layer is employed as the source contact. A high uniformity of the device characteristics for numerous transistors is further presented and RF characterization of these devices demonstrates an f(t) of 9.8 GHz.     

Single-crystalline branched zinc phosphide nanostructures: synthesis, properties, and optoelectronic devices

Hierarchical tree-shaped nanostructures, nanobelts, and nanowires of Zn3P2 were synthesized in a thermal assisted laser ablation process. All nanostructures are tetragonal phased Zn3P2 with excellent crystallinity and are free from an oxidization layer according to electron microscopy and X-ray diffraction analyses. Optical measurement revealed a strong absorption from the ultraviolet to near-infrared regions. Optoelectronic devices fabricated using individual nanowires demonstrate a high sensitivity and rapid response to impinging light. A crossed heterojunction of an n-type ZnO nanowire and a p-type Zn3P2 nanowire has been characterized, and it offers a great potential for a high efficient spatial resolved photon detector.     

Conductance, surface traps, and passivation in doped silicon nanowires

We perform ab initio calculations within the Landauer formalism to study the influence of doping on the conductance of surface-passivated silicon nanowires. It is shown that impurities located in the core of the wire induce a strong resonant backscattering at the impurity bound state energies. Surface dangling bond defects have hardly any direct effect on conductance, but they strongly trap both p- and n-type impurities, as evidenced in the case of H-passivated wires and Si/SiO2 interfaces. Upon surface trapping, impurities become transparent to transport, as they are electrically inactive and do not induce any resonant backscattering.     

High cadmium-109 recovery from a dissolved silver target solution using dowex 1×8 anion-exchange resin

Separation of ¹⁰⁹Cd produced by proton irradiation of a silver target from the target material and the other products was achieved. Radiochemical separation of ¹⁰⁹Cd from silver and nonisotopic impurities involves two steps: precipitation and ion exchange. The dissolved target material solution is evaporated almost to dryness. The residue is dissolved in 0.015 M HCl, with quantitative precipitation of silver from the solution. In the second step, ¹⁰⁹Cd is separated from Cu and ⁶⁵Zn on an anion-exchange column (Dowex 1×8). ¹⁰⁹Cd is completely retained in the column, whereas copper and more than 70% of ⁶⁵Zn pass through during loading the solution. ¹⁰⁹Cd is then eluted from the column with 0.5 M HNO₃. High recovery of ¹⁰⁹Cd (99.77%) with 2.1% ⁶⁵Zn impurity was attained.     

Direct atomic scale imaging of III-V nanowire surfaces

We have succeeded in direct atomic scale imaging of the exterior surfaces of III-V nanowires by scanning tunneling microscopy (STM). By using atomic hydrogen, we expose the crystalline surfaces of InAs nanowires with regular InP segments in vacuum while retaining the wire morphology. We show images with atomic resolution of the two major types of InAs wurtzite nanowire surface facets and scanning tunneling spectroscopy (STS) data. Ab initio calculations of the lowest energy surface structures and simulated STM images, agree very well with experiments.     

Boron and aluminum diffusion into 4H-SiC substrates

Boron and aluminum doping by diffusion into n-type 4H-SiC Si-face substrates was carried out at the temperatures of 1800-2000 °C. Secondary ion mass spectroscopy (SIMS) was employed to obtain the impurity profiles, which showed that linearly graded boron profile and shallow aluminum profiles have been achieved, which may be a promising application in SiC device fabrication, such as p-n diode or ohmic contact. Characterization of high temperature processing influence on SiC surface morphology has been performed. Elemental boron and aluminum carbide were determined to be the best candidates as an impurity source materials for realizing p-type diffusion.