无线NoC研究与进展

分析了无线NoC的一般结构,对两种典型拓扑结构及其相关特性进行了比较,并对无线NoC涉及到的关键通信机制,特别是片上天线、路由及通信协议对其性能的影响进行了讨论,最后对未来无线NoC的技术热点及难点问题进行了总结和展望。     

片上网络中3D拓扑结构的性能评估

3D结构的片上网络(3D NoC)结合了3D集成(3D IC)和NoC技术的优势,相比2D NoC具有更为优越的性能.然而,目前大多数关于3D NoC结构的研究都集中在3D Mesh结构上.介绍了利用NIRGAM仿真器实现的另一种拓扑结构--3D Torus.在均衡负载模式和对称随机负载模式下分析评价了3D Torus网络延迟和吞吐率.结果表明,3D Torus拓扑结构的性能高于3D Mesh结构.     

基于FPGA的NoC路由节点的设计

在对NoC设计技术进行研究的基础上,建立满足要求的NoC路由节点模型,该模型采用规则的2D-Mesh拓扑结构,基于虚通道技术的虫洞数据交换方式以及无死锁的确定性XY维路由算法实现.用硬件描述语言Veril-og完成各部分的功能设计,在ModeSim仿真软件下进行功能仿真,并且在基于FPGA的NoC系统上实现了路由节点的功能.     

一种自适应的混合型无线NoC拓扑结构

针对传统大规模片上网络（Network-on-Chip,NoC）远距离核间多跳通信所带来的高能耗与延时问题,提出了一种基于虚Torus的自适应的混合型无线NoC拓扑结构（VT-AWiNoC）．该结构通过引入链路拥塞测度作为感知参数,基于此采用热点无线链路自动探测与带宽动态分配机制,并设计实现发送器动态分配的控制电路模块,以达到根据不同的通信流量模型,于片内自适应地调整拓扑结构及链路带宽的目的．通过建立混合型无线NoC的延时与功耗评估模型,对该结构的无线NoC进行性能评估．实验结果表明,该自适应拓扑与其它混合型无线NoC相比,在随机流量模型下,网络平均延时降低了16．52～23．27％;在20％的热点流量模型下,包平均能耗节省了39．19％;以真实应用FFT作为基准测试,平均延时降低了17．20％～21．68％,并节省了23．49％的包平均能耗．该结构以较小的面积开销获得了更优的性能．     

面向无线NoC平台的拓扑与映射联合设计

传统NoC映射算法基于拓扑是确定的,无法为具体应用动态选择最优拓扑.无线NoC具有互联简单、低功耗、低延时、多播和动态带宽分配等突出优点.利用灵活的网络接入特性,提出面向无线NoC平台的拓扑与映射联合设计算法,采用改进的能耗模型,结合实时复杂系统特有的注入率、迭代边界等约束,以最小化延时和功耗为目标,同时对拓扑和映射进行优化.通过对无线通信系统——MIMO-OFDM收发端进行建模与仿真,证明该算法较之传统映射算法有明显的性能提升.     

不规则2D Mesh NoC映射算法研究

片上网络(NoC)因其分层通讯结构而有望成为未来动态重构片上系统的支撑技术,针对复杂片上系统中可能集成各种规模IP的实际情况,对不规则2D mesh拓扑结构的NoC进行了研究,建立了其映射算法的数学模型和优化目标函数,提出了保证网格不重叠约束条件的数学表达和IP间通信距离的求解方法,采用一个视频解码器实例,给出了映射算法模拟结果和分析,并探讨了布局结果的FPGA实现.     

基于分组网络结构NoC的BIST串扰测试方法

针对大规模NoC芯片设计中BIST测试时间长和消耗面积大的问题,提出一种测试NoC内switch间互连线串扰的BIST方法。对于互连线工作在1 GHz以下的大规模NoC,电容耦合是影响串扰的主要因素。通过并行测试结构,同时对几条受害线进行测试,有效减小了测试时间和电路面积。从理论角度对所提方法的测试时间和功率损耗进行了分析,以3×3 mesh结构的NoC为例,验证了所提方案和理论分析的正确性。     

NoC功耗与性能的研究

在当前高性能片上网络设计中,功耗和延迟是设计所面临的核心问题之一。在此着重阐述了构成低功耗和低延迟NoC的4种结构:低摆幅的信号传输结构、可重构的NoC结构、3D的IC设计结构、基于数据压缩机制的结构。通过对其功过原理的分析,比较了4种结构的优缺点,最后对未来低功耗、低延迟的NoC发展方向做出了预测。     

一种分层结构的片上网络路由设计

随着同一芯片中处理器数日的不断增加,层次化网络结构将成为片上网络(NoC)拓扑研究的热点.针对典型的NoC不规则分层拓扑结构,设计了一套新的免死锁混合路由算法以及新的节点编址方式.同时提出了一种新的交换节点设计构想,并给出了一种有效的拥塞控制策略.仿真结果表明,当网络中数据流量变大时分层网络比传统二维网络具有更小的传输时延以及更大的吞吐量.     

三相功率因数校正电路拓扑结构的研究

介绍了三相功率因数校正电路几种主要的拓扑结构——三相单开关功率因数校正电路、三相两开关PFC电路、三相三开关PFC电路、三相四开关PFC电路等;并分析了每种拓扑结构的特性、优点以及缺点,应用MATLAB软件对其中部分电路做了仿真。     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

An interconnection architecture for network-on-chip systems

Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.     

片上网络节点编码的设计和在路由方面的应用

网络拓扑选择和路由算法设计是片上网络设计的关键问题.在比较现有的三种网络拓扑结构的基础上,提出了一种隐含着相邻节点以及节点之间链路关系并适合二维Torus拓扑结构的节点编码方法.该编码和Torus结构的结合能拓扑结果够简化路由算法的设计和实现,改善了网络路由性能.实验结果表明,提出的编码方法与二维Torus拓扑结构的结合有效地提高了片上网络通信性能.     

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.     

连接圭从IP核的片上网络路由器结构

随着单个芯片上集成的元器件数目不断增加,功耗问题也变得越来越突出。片上网络虽然能够从理论上解决传统总线结构带来的种种问题,但其功耗问题在某些具体应用中却变成了关键的制约因素。路由器作为片上网络的核心部件,其结构直接影响片上网络的性能。路由器的功耗问题已经成为片上网络领域一个热点问题。本文运用最优化理论对连接主从IP核的片上网络路由器结构进行优化设计,并运用路由器的功耗模型对功耗问题进行了分析。最后运用OPNET仿真软件对路由器的交换机制和路由算法进行分析对比,得出最终结论。     

HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms

This paper presents design, development and evaluation of an eXtra-large Scale, Homogeneous and a Heterogeneous Accelerator-Rich Platform (HARP²) for massively parallel signal processing algorithms. HARP is an integrated platform of multiple Coarse-Grained Reconfigurable Arrays (CGRAs) over a Network-on-Chip (NoC) where each CGRA is scaled and tailored for a specific application. The architecture of the NoC consists of nine nodes in a topology of 3-rows × 3-columns and acts as backbone of communication between different CGRAs. In this experimental work, the HARP template is used to instantiate a homogeneous (HARP-hom) and a heterogeneous (HARP-het) platform. The HARP-het is generated for a proof-of-concept test to verify the design and functionality of HARP. It also provides insight to many features of the design and evaluation in terms of different performance metrics. The other version (HARP-hom) is instantiated for a relatively realistic design problem, i.e., satisfying the execution-time constraints imposed on Fast Fourier Transform processing in IEEE-802.11n demodulators. Both of the versions of HARP are treated for comparative analysis using different performance metrics against some of the existing state-of-the-art platforms. The HARP versions are designed to illustrate large-scale homogeneous/heterogeneous multicore architectures while presenting the advantages of maximizing the number of reconfigurable processing resources on a single chip.     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.      

Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.     

片上网络调度算法相关研究

随着半导体集成工艺的发展,单个芯片上集成的IP核数目急剧增加,片上网络(NoC)成为未来取代总线设计的新模式。调度算法作为NoC研究的关键问题之一,对整个网络的传输性能起着重要的作用。本文对片上网络虚信道路由器调度算法的相关研究进展进行了总结,首先从路由器结构特点出发,介绍了几种典型的NoC仲裁器和调度器实例,总结相应的算法设计思想。再对NoC常用路由器调度算法进行了分类介绍,详细分析了各种调度算法的相关特性。最后,探讨了NoC路由器调度算法的研究方向。