0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。     

一种低功耗14位10MS/s流水线A/D转换器

基于0.6μm BiCMOS工艺,设计了一个低功耗14位10MS/s流水线A/D转换器.采用了去除前端采样保持电路、共享相邻级间的运放、逐级递减和设计高性能低功耗运算放大器等一系列低功耗技术来降低ADC的功耗.为了减小前端采样保持电路去除后引入的孔径误差,采用一种简单的RC时间常数匹配方法.仿真结果表明,当采样频率为10MHz,输入信号为102.5kHz,电源电压为5V时,ADC的信噪失真比(SNDR)、无杂散谐波范围(SFDR)、有效位数(ENOB)和功耗分别为80.17dB、87.94dB、13.02位和55mW.     

A 10-b 50 MS/s 500-mW A/D converter using a differential-voltagesubconverter

A BiCMOS A/D converter using a “differential voltage subconverter,” which directly converts a voltage difference of complementary analog inputs to a digital code, is described. Fully differential architecture has advantages in immunity of common-mode error and in reduction of supply voltage. This differential-voltage subconverter realizes the fully differential A/D conversion without using interpolation technique. This subconverter is free from CR delay caused in the ladder resistors. Circuit techniques for high-accuracy conversion with single 5-V power supply, such as compensation technique for VBE modulation in emitter degeneration amplifier, are also described. A 10-b A/D converter is fabricated in a 0.8-μm BiCMOS process with f_T of 9 GHz. It successfully operates at 50 MS/s with 500-mW power consumption and with 5-V single supply     

一种低压BiCMOS四象限模拟乘法器的设计

提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。     

A single-power-supply 10-b video BiCMOS sample-and-hold IC

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2-μm BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW     

A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm×5.6-mm ADC chip was fabricated using a 0.8-μm BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply     

A 10-GHz SiGe BiCMOS phase-locked-loop frequency synthesizer

A SiGe BiCMOS phase-locked-loop (ILL) circuit is presented. A maximum operational frequency of 10 GHz and a current consumption of 7.6 mA, i.e., 17 mW, is demonstrated. For a 9-mW low-power version, a maximum frequency of 4.7 GHz is determined. In a GSM direct conversion application, an in-band phase noise of -79 dBc/Hz at 2 kHz and a spurious suppression of -75 dBc at 400 kHz was measured at 3.4 GHz, which corresponds to a PLL phase noise floor of -214 dBc/Hz. For low-power applications, the PLL can be operated at supply voltages as low as 2.2 V and at RF input powers as low as -20 dBm while having a large output voltage range of 0.2 V to (V_cc-0.3 V). This demonstrates the speed and power advantage of the SiGe BiCMOS over Si BiCMOS and CMOS technologies for wireless communications     

A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator

An ultra-low-power, 2$ ^7-$1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz$f_T$SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method.     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

Study of BiCMOS logic gate configurations for improved low-voltageperformance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C     

A 6-GHz Low-Power BiCMOS SiGe:C 0.25 μ m Direct Digital Synthesizer

A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This letter discusses the BiCMOS design improvements used for the phase accumulator and the phase-to-amplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 mum technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm².     

Low-power BiCMOS circuits for high-speed interchip communication

A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Using a 3.3 V supply, the novel transceiver can drive/receive signals from several low-voltage-swing transceivers with termination voltages ranging from 5 V down to 2 V and frequencies well above 1 GHz. Measured results of test circuits fabricated in 0.8-μm BiCMOS technology are also presented     

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-MbDRAM's

A 0.3-μm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design     

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 m BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured –3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 W. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.     

新型的芯片间互连用CMOS/BiCMOS驱动器

从改善不同类型 IC芯片之间的电平匹配和驱动能力出发 ,设计了几例芯片间接口 (互连 )用 CMOS/Bi CMOS驱动电路 ,并提出了采用 0 .5 μm Bi CMOS工艺 ,制备所设计驱动器的技术要点和元器件参数。实验结果表明所设计驱动器既具有双极型电路快速、大电流驱动能力的特点 ,又具备 CMOS电路低压、低功耗的长处 ,因而它们特别适用于低电源电压、低功耗高速数字通信电路和信息处理系统。     

可自校正失调电压的BiCMOS锁存比较器设计

在对传统CMOS锁存比较器分析的基础上,设计了一种可自校正失调电压的BiCMOS锁存比较器,它既具有双极型电路快速、输入失调电压低和大电流驱动能力,又具备CMOS电路低功耗和高集成度的特性,因而它们特别适用于高速缓冲数字信息系统和其它便携式数字设备.     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

Integrated on-chip 0.35 μm BiCMOS current-mode DC–DC buck converter

A current-mode DC–DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC–DC converter is fabricated with 0.35?µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3?MHz switching frequency with a supply voltage of 5?V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30?µH off-chip inductor and 100?µF off-chip capacitor.     

全差分BiCMOS采样/保持电路仿真设计

在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。