High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

Positive flatband voltage shift in MOS capacitors on n-type GaN

GaN MOS capacitors were fabricated using silicon dioxide deposited by low-pressure chemical vapor deposition oxide at 900°C. The MOS capacitor flatband voltage shift versus temperature was used to determine a pyroelectric charge coefficient of 3.7 × 10⁹ q/cm²-K, corresponding to a pyroelectric voltage coefficient of 7.0 × 10⁴ V/m-K     

High-performance p-channel poly-Si TFT's using electron cyclotronresonance hydrogen plasma passivation

This letter presents a summary of the first detailed investigation of electron cyclotron resonance (ECR) hydrogen plasma exposure treatments of p-channel poly-Si thin film transistors (TFT's). It is shown that ECR hydrogenation can be much more efficient than RF hydrogenation. Poly-Si p-channel TFT's fabricated at low temperatures (⩽625°C) and passivated with the ECR hydrogenation treatment are shown to exhibit ON/OFF current ratios of 7.6×10⁷, subthreshold swings of 0.62 V/decade, threshold voltages of -4.6 V, and hole mobilities over 18 cm²/V.s     

Power performance of InP-based single and double heterojunctionbipolar transistors

The microwave and power performance of fabricated InP-based single and double heterojunction bipolar transistors (HBTs) is presented. The single heterojunction bipolar transistors (SHBTs), which had a 5000 Å InGaAs collector, had BV_CEO of 7.2 V and J_Cmax of 2×10⁵ A/cm². The resulting HBTs with 2×10 μm² emitters produced up to 1.1 mW/μm2 at 8 GHz with efficiencies over 30%. Double heterojunction bipolar transistors (DHBTs) with a 3000-Å InP collector had a BV_CEO of 9 V and J_{c max} of 1.1×10⁵ A/cm², resulting in power densities up to 1.9 mW/μm² at 8 GHz and a peak efficiency of 46%. Similar DHBTs with a 6000 Å InP collector had a higher BV_CEO of 18 V, but the J _{c max} decreased to 0.4×10⁵ A/cm² due to current blocking at the base-collector junction. Although the 6000 Å InP collector provided higher f_max and gain than the 3000 Å collector, the lower J_{c max} reduced its maximum power density below that of the SHBT wafer. The impact on power performance of various device characteristics, such as knee voltage, breakdown voltage, and maximum current density, are analyzed and discussed     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

10 A, 2.4 kV Power DiMOSFETs in 4H-SiC

We report the characteristics of large area (3.3 × 3.3 mm ²) high-voltage 4H-SiC DiMOSFETs. The MOSFETs show a peak MOS channel mobility of 22 cm²/V·s and a threshold voltage of 8.5 V at room temperature. The DiMOSFETs exhibit an on-resistance of 4.2 mΩ·cm² at room temperature and 85 mΩ·cm² at 200°C. Stable avalanche characteristics at approximately 2.4 kV are observed. An on-current of 10 A is measured on a 0.103 cm² device. High switching speed is also demonstrated. This suggests that the devices are capable of high-voltage, high-frequency, low-loss switching applications     

Carrier transport related analysis of high-power AlGaN/GaN HEMTstructures

Shubnikov-de Haas (SdH) oscillation and Hall measurement results were compared with HEMT DC and RF characteristics for two different MOCVD grown AlGaN-GaN HEMT structures on semiinsulating 4H-SiC substrates. A HEMT with a 40-nm, highly doped AlGaN cap layer exhibited an electron mobility of 1500 cm²/V/s and a sheet concentration of 9×10¹² cm at 300 K (7900 cm²/V/s and 8×10¹² cm^-2 at 80 K), but showed a high threshold voltage and high DC output conductance. A 27-nm AlGaN cap with a thinner, lightly doped donor layer yielded similar Hall values, but lower threshold voltage and output conductance and demonstrated a high CW power density of 6.9 W/mm at 10 GHz. The 2DEG of this improved structure had a sheet concentration of n_SdH=7.8×10¹² cm^-2 and a high quantum scattering lifetime of τ_q=1.5×10^-13 s at 4.2 K compared to n_SdH=8.24×10¹² cm^-2 and τ_q=1.72×10^-13 s for the thick AlGaN cap layer structure, Despite the excellent characteristics of the films, the SdH oscillations still indicate a slight parallel conduction and a weak localization of electrons. These results indicate that good channel quality and high sheet carrier density are not the only HEMT attributes required for good transistor performance     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

KrF excimer laser annealed TFT with very high field-effect mobilityof 329 cm2/V-s

A thin-film transistor (TFT) with a maximum field-effect mobility of 320 cm²/V-s, an on/off current ratio of 7.6×10⁷ , a threshold voltage of 6.7 V and a subthreshold slope of 0.37 V/decade was fabricated by using pulse laser annealing processes. Amorphous silicon films (a-Si:H) with a very low impurity concentration of 4×10¹⁸ cm^-3 for oxygen, 1.5×10¹⁸ cm^-3 for carbon, and 2×10¹⁷ cm^-3 for nitrogen were deposited by a plasma chemical vapor deposition (CVD) method and annealed by KrF excimer laser (wavelength of 248 nm). The Raman spectroscopy technique was a useful tool for optimizing laser annealing conditions. Experimental results show that two factors are very important for fabricating very-high mobility TFTs: (1) utilizing high-purity as-deposited a-Si:H film; and (2) performing whole laser annealing processes sequentially in a vacuum container and optimizing illumination conditions     

Steady-state and transient forward current-voltage characteristicsof 4H-silicon carbide 5.5 kV diodes at high and superhigh currentdensities

Steady-state and transient forward current-voltage I-V characteristics have been measured in 5.5 kV p⁺-n-n⁺ 4H-SiC rectifier diodes up to a current density j≈5.5×10 ⁴ A/cm². The steady-state data are compared with calculations in the framework of a model, in which the emitter injection coefficient decreases with increasing current density. To compare correctly the experimental and theoretical results, the lifetime of minority carriers for high injection level, τ_ph, has been estimated from transient characteristics. At low injection level, the hole diffusion length L_pl has been measured by photoresponse technique. For a low-doped n-base, the hole diffusion lengths are L_pl≈2 μm and L_ph≈6-10 μm at low and high injection levels respectively. Hole lifetimes for low and high injection levels are τ_pl≈15 ns and τ_ph≈140-400 ns. The calculated and experimental results agree well within the wide range of current densities 10 A/cm ²3 A/cm². At j>5 kA/cm², the experimental values of residual voltage drop V is lower than the calculated ones. In the range of current densities 5×10³ A/cm²4 A/cm², the minimal value of differential resistance R_d =dV/dj is 1.5×10^-4 Ω cm². At j>25 kA/cm², R_d increases with increasing current density manifesting the contribution of other nonlinear mechanisms to the formation steady-state current-voltage characteristic. The possible role of Auger recombination is also discussed     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

Low-noise back-illuminated AlxGa1-xN-basedp-i-n solar-blind ultraviolet photodetectors

We report the growth, fabrication and characterization of Al_0.4Ga_0.6N-Al_0.6Ga_0.4N back-illuminated, solar-blind p-i-n photodiodes. The peak responsivity of the photodiodes is 27 and 79 mA/W at λ≈280 nm for bias voltages of 0 V and -60 V, respectively, with a UV-to-visible rejection ratio of more than three decades (at 400 nm). These devices exhibit very low dark current densities (~5 nA/cm² at -10 V). At low frequencies, the noise exhibits a 1/f-type behavior. The noise power density is S₀≈5×10^-25 A²/Hz at -12.7 V and the detectivity (D*) at 0 V is estimated to be in the range of 4×10¹¹-5×10¹³ cm·Hz^1/2 /W. Time-domain pulse response measurements in a front-illumination configuration indicate that the devices are RC-time limited and show a strong spatial dependence with respect to the position of the incident excitation, which is mainly due to the high resistivity of the p-type Al_0.4Ga_0.6 N layer     

Polycrystalline silicon thin film transistors fabricated at reducedthermal budgets by utilizing fluorinated gate oxidation

Polycrystalline silicon thin film transistors have been fabricated at reduced gate oxidation thermal budgets by utilizing NF₃-enhanced dry oxidation. Good performance TFTs with effective electron mobility values as high as 38 cm²/V.sec, threshold voltage values near zero, ON/OFF current ratios of up to 5×10⁷ and subthreshold slopes of 0.3 V/dec have been fabricated at an oxidation temperature of 800°C. Stable devices at an electrical stressing field of 3 MV/cm were demonstrated. Thermal gate oxide TFTs have also been fabricated at a maximum temperature of 650°C. The effect of hydrogen plasma passivation was found to depend on process conditions and was correlated with the amount of fluorine in the area near the Si-SiO₂ interface. Passivation at low power was always beneficial. Passivation at high power was highly beneficial for a limited amount of interfacial fluorine, but less beneficial or even detrimental when a large fluorine amount in the near interface area was present     

Fabrication of planar optical waveguides in LiB3O5 by 2 MeV He+ ion implantation

The fabrication of planar optical waveguides in LiB₃O ₅ is discussed. Using 2-MeV ⁴He⁺ implantation with a dose of 1.5×10¹⁶ ions/cm² at 300 K, the refractive indexes of a 0.2-μm-thick layer 5.1 μm below the crystal surface are reduced to form optical barrier guides. For this ion dose the maximum change from the bulk values of refractive index at a wavelength of 0.488 μm are 1.5%, 5.25%, and 4% for n_x, n_y, and n_z, respectively. The refractive indexes of the guiding region change by less than 0.02% from the bulk values. The dose dependence of the optical barrier height has been measured. A threshold ion dose of about 0.75×10¹⁶ ions/cm² is required to form a refractive index barrier and ion doses higher than about 2.5×10¹⁶ ions/cm². saturate the refractive index decrease. Waveguide propagation losses for annealed single energy implants of dose 1.5×10¹⁶ ions/cm² are dominated by tunneling and are estimated to be ~8.9 dB/cm for the z-cut waveguides used. Multiple energy implants broaden the optical barrier, and losses of <4 dB/cm have been observed