Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

The threshold-voltage model of MOSFET devices with localizedinterface charge

A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation. Calculating the minimum surface potential, the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for both fresh and damaged devices. Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage. Calculation results show that the extension, position and density of localized interface charge are the main issues influencing the threshold voltage of a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreement is obtained for various cases     

Numerical analysis of silicon-on-lnsulator short channel effects in a radiation environment

Radiation-induced charge build-up in the buried oxide (BOX) of SOI MOSFETs affects device performance through threshold voltage shifts of the back channel. This charge build-up is related to the electric field in the BOX during irradiation. In this paper, we report on the application of a numerical model for the potential distribution in a semiconductor device to the task of determining the electric field in the BOX. This electric field distribution is then combined with a model for charge accumulation as a function of electric field during irradiation to predict the threshold voltage shifts in the back channel of SOI MOSFET devices as a function of channel length. For the device design analyzed here, this model agrees with available experimental data and predicts an increase in back channel threshold shift as the channel length enters the sub-micron regime.     

深亚微米SOI栅控混合管(GCHT)的准二维电流解析模型

提出了深亚微米SOIGCHT电流模型.不同于普通MOSFET短沟模型的处理,计及受栅电压及基极电压同时控制的可动电荷的影响,采用准二维分析及抛物线近似,求出沟道长度及漏端电压对源端表面势的影响,较好地反映了电荷共享效应及DIBL效应,并定量计算出与漏电压和栅电压同时相关的动态阈值电压漂移量.模型中同时考虑了速度饱和效应、迁移率下降效应和沟道长度调制效应等.该模型具有清晰的物理意义,从理论上解释了GCHT具有较小的短沟效应及较高的阈值电压稳定性等物理现象.模型计算结果与数值模拟及实验结果吻合良好,较好地描述了短沟GCHT的物理特性.     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.     

Non-ionic room temperature instabilities in MOS devices

Recently it has been pointed out that considerable instabilities can occur in MOS devices under negative voltage bias at room temperature. These instabilities are observed by appling at room temperature a voltage to the gate of an MOS device, cooling under this voltage bias to 77°K and subsequently measuring the CV curve or the threshold voltage with the applied voltage bias as parameter. The instabilities are due to the generation of positive charges in the oxide and cause negative voltage shifts. The generation of positive charges appears to be due to two types of centres (type 1 and type 2). Whereas the charge in the type 2 centres is stable at 77°K, the charge in the type 1 centres disappears at 77°K as soon as free electrons are present at the surface. Furthermore there is an increased fast interface state density, which is closely related to the positive charge in the type 2 centres.

In this paper the charging of both centres is described in terms of a thermally assisted tunnelling process. In this way the observed time and temperature dependencies of the charging are explained and activation energies are determined. A model is presented that explains among other things the different discharge behaviour of the type 1 and type 2 centres.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

关态应力下P-MOSFETs的退化

研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs＝0,Vds＜0)下的热载流子效应．讨论了开态和关态应力．结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小．但是低场应力后关态漏电流会增加,这是由于新生界面态的作用．结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响．Idsat的退化可以用函数栅电流（Iｇ）乘以注入的栅氧化层电荷数（Qinj）的幂函数表达．最后给出了基于Idsat退化的寿命预测模型．     

Characterization, modeling, and minimization of transient thresholdvoltage shifts in MOSFETs

MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO₂ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented     

An analysis of the threshold voltage for short-channel IGFET''s

For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length.

The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G/sup 4/-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G/sup 4/-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices.     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

A closed-form trapped-charge-included drain current compact model for amorphous oxide semiconductor thin-film transistors

A closed-form drain current compact model for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), including the influence from trapped charges, is presented in this paper. Accounting for both channel and interface trapped charges in this model, we explicitly solve the inherent closed-form surface potential by improving the computational efficiency of the effective charge density approach. Furthermore, based on the explicit solution of the surface potential, the expressions of the trapped and inversion charges in the channel film are derived analytically, and the drain current is integrated from the charge sheet model. Then, for the cases of the different operational voltages, the accuracy and practicability of our model are verified by numerical results of the surface potential and experimental data of the drain current in amorphous In-Ga-Zn-O TFTs, respectively. Finally, we give a discussion about the influence of the interface trapped charges on the device reliability. As a result, the model can be easily to explore the drain current behavior of the AOS TFTs for next-generation display circuit application.     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Threshold shift calculations for ion implanted MOS devices

The solutions of Poisson's equation applicable to ion implanted MOS devices have been used to generate capacitance-voltage relationships for capacitors and threshold voltage shifts for transistors. The calculations agree well with previously published transistor data for profiles centered near Si-SiO₂ interface. These shallow implants (< 0.1 μm) are easily controlled by the gate and yield voltage shifts equal to that expected for all of the charge lumped at the silicon surface. In addition, the observed saturation of gate voltage shift for deeper implants in enhancement mode transistors can be duplicated by the calculations provided that the stopping power of SiO₂ is reduced as has been proposed elsewhere. Further, it has been predicted that gate control will be lost for depletion mode transistors with sufficiently deep implants. This is caused by the formation of a deep channel which is isolated from gate control by an induced surface charge layer. The inability of the gate field to pinch off the channel defeats device use for transistor inverter loads.     

Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

A two-dimensional numerical solution of electrostatic potential and electric field profiles are presented for lightly doped nano-scale Double-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistor (DG-MOSFET). We have developed quasi-static (QS) model for evaluating bulk and inversion charges based on symmetric linearization model. We have also shown the non-quasi-static (NQS) effect on the charge due to a time varying gate voltage. It is seen that various symmetries of DG-MOSFET characteristics with respect to source/drain interchange is maintained in quasi-static as well as non-quasi-static version of the symmetrically linearized model. The variation of the threshold voltage with the varying width of the device is evaluated and presented. The results have been compared and contrasted with reported analytical model for QS condition for the purpose of verification of the model. The variation of threshold voltage along the width of the device is also predicted. This numerical model can be extended to analyze the transport phenomenon in sub 30 nm channel length DG-MOSFETs.     

A new quantitative model for weak inversion charge injection inMOSFET analog switches

This paper proposes a new model concerning the channel charges in weak inversion injected from a turn-off MOSFET into a holding capacitor. This portion of charge injection has recently been newly observed, showing a significant contribution to the switch-induced error voltage on the switched capacitor. Our model is derived at the critical point where the device is operated in the transition region between strong inversion and weak inversion. This point has been expressed explicitly as a function of the DC input voltage, the threshold voltage, and the fall time of the gate voltage. The ability of the model in accurately determining quantitatively the impact of the weak inversion charge injection on the error voltage has been extensively judged experimentally and by two-dimensional mixed-mode simulation for a wide variety of design parameters such as the channel width and length, the holding capacitance, the fall time of the gate voltage, and the DC input voltage The assumptions utilized in the model development have also been validated     

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas (2DEG) density and surface potential for AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMT). The developed model includes important parameters like polarization charge density at oxide/AlGaN and AlGaN/GaN interfaces, interfacial defect oxide charges and donor charges at the surface of the AlGaN barrier. The effects of two different gate oxides (Al₂O₃ and HfO₂) are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al₂O₃ dielectric have an advantage of significant increase in 2DEG up to 1.2×10¹³ cm^-2 with an increase in oxide thickness up to 10 nm as compared to HfO₂ dielectric MOSHEMT. The surface potential for HfO₂ based device decreases from 2 to -1.6 eV within 10 nm of oxide thickness whereas for the Al₂O₃ based device a sharp transition of surface potential occurs from 2.8 to -8.3 eV. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model, the device is simulated in Silvaco Technology Computer Aided Design (TCAD) showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for GaN MOSHEMT devices for performance analysis.