Lucky-electron model of channel hot-electron injection in MOSFET'S

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.     

A simple model for short channel MOSFET's

A model for short channel MOSFET's is presented. The model is simple in spite of taking 2-dimensional (2-D) effects into account. Predicted I-V characteristics are in good agreement with experimental results. This model can be utilized in circuit analysis programs.     

Analysis of the gate-voltage-dependent series resistance of MOSFET's

The intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed. This new model includes the effects due to the unavoidable doping gradient near the metallurgical junction. It is assumed that current first conducts through the accumulation layer before spreading into the bulk region, and thus the spreading (injection) resistance and the accumulation layer resistance have to be considered in series and both are gate-voltage dependent. More importantly, they are shown to be a strong function of the steepness of the doping profile. The model quantitatively predicts these resistance components for a given process, and it emphasizes the necessity for a steep junction profile in order to minimize the series resistance of MOSFET's.     

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.     

Estimation of doping profiles in short channel MOSFET's using DC Measurements

Estimation of impurity profiles in short channel enhancement-mode MOSFET's using the dc measurement technique is studied. The use of long channel theory predicts erroneous impurity profiles for devices with channel lengths of less than 6 µm. A new empirical model for substrate charge sharing is presented which provides good agreement between profiles estimated by measurements on identically doped long and short channel MOSFET's. It is found that the dc measurement technique can be extended to enhancement-mode MOSFET's with channel lengths as small as 2.5 µm.     

A calibrated model for the subthreshold operation of a short channel MOSFET including surface states

Describes a simple two-dimensional subthreshold model for short channel MOSFET's. The effects of surface state density are also included in the model. A regional charge density approximation was used in the solution of Poisson's equation and an analytical solution of the continuity equation in two dimensions was derived. Excessive computations are avoided in the present model; this was made possible by the use of a valid regional charge approximation. The model was experimentally verified by performing measurements on short channel devices. The model was calibrated from measurements on a long channel device which was present on the same silicon chip. Results are presented for the subthreshold leakage current as a function of substrate bias, polysilicon gate length, diffusion depth and surface state density.     

A simple analytical model for the electrical characteristics of depletion-mode MOSFET's with application to low-temperature operation

A simple analytical model for depletion-mode MOSFET's is developed based on the gradual channel approximation and taking into account carrier freeze-out onto impurity sites implanted for threshold voltage modification. Theory is found to be in reasonable agreement with experimental results for n-channel depletion-mode MOSFET's at room temperature and at 77 K. It is shown that the common methods used for enhancement-mode devices to determine carrier channel mobility and threshold voltage, respectively, from the slope and voltage intercept of the current-gate voltage characteristics are invalid for depletion-mode devices. By comparison of enhancement and depletion devices on the same chip, it is shown that the processes associated with ion implantation had no effect on electron channel mobility at room temperature and caused at most a 25-percent reduction at 77 K. The model also is applicable to buried p-channel devices as used in CMOS technologies.     

On the accuracy of channel length characterization of LDD MOSFET's

A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n^-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFET's. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFET's.     

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

2D numerical investigation of the impact of compositional gradingon the performance of submicrometer Si-SiGe MOSFET's

Computer simulation is used to establish the impact of design parameters on the subthreshold characteristics, hot carrier injection, and high frequency performance of Si-SiGe FET's. The results indicate that by fully grading the Ge content in the channel of a MOSFET, short channel effects are reduced and high frequency performance is improved as compared to devices with uniform Ge channels. A cutoff frequency of 38 GHz and a maximum frequency of oscillation of 160 GHz are predicted for fully graded p-channel MOSFET's with 0.25 μm gate lengths. Energy balance simulation reveals that hot carrier injection at the Si-SiO₂ interface is considerably suppressed if a fully graded channel is employed     

Relationship between MOSFET degradation and hot-electron-induced interface-state generation

Device degradation due to hot-electron injection in n-channel MOSFET's is mainly caused by mobility degradation and reduced mobile charges in the channel introduced by interface-state generation. With the use of simple gradual-channel approximation (GCA), a linear relationship is derived between the threshold shift, relative transconductance reduction, and the number of interface states generated. This model provides a link between the electrical characteristics of a degraded device and its physical damages and, therefore, is a vital tool in the study of hot-electron-induced device degradation mechanisms.     

An accurate intrinsic capacitance modeling for deep submicrometerMOSFET's

This paper presents a new approach to the modeling of MOSFET capacitive characteristics for accurate simulation of deep submicrometer integrated circuits. The C-V characteristics of our new quasistatic intrinsic capacitance model accurately describes the short channel effects of deep submicrometer MOSFET's by accounting for velocity saturation and series resistance effects. The use of charge equations consistent with the short channel I-V characteristics leads to C-V characteristics which preserve all major short channel effects. The C-V calculation, based on nonpinned surface potential approach and drift-diffusion model, shows highly accurate short-channel effects and inherently smooth transitions for all conditions of device operation. The accuracy of the C-V characteristics has been demonstrated by comparison with the Ward-Dutton model and PISCES simulation results     

Nonscaling of MOSFET's linear resistance in the deep submicrometerregime

This paper investigates the scaling properties of deep submicron MOSFET's and shows that, while in a wide range of channel lengths they can be represented as composed by a scaling intrinsic and a nonscaling parasitic part, this picture does no longer hold for shorter transistors. A nonscaling of the total resistance R_TOT=[V_DS/I_DS] of short devices is observed, and its impact on parasitic resistances and effective channel length extraction is discussed. A possible explanation is suggested in relation to the two-dimensional substrate doping redistribution linked to reverse-short-channel effects     

MOSFET thermal noise modeling for analog integrated circuits

The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements     

Hot hole induced interface state generation and annihilation in SOIMOSFETs

The effects of pure hot hole injection in SOI MOSFET's are investigated. Pure hot hole injection is achieved by exploiting the opposite channel based carrier injection phenomenon. It is found that significant amounts of interface states are generated, some of which are annihilated by a subsequent hot electron injection pulse. A power law of the form D_it(t)=Ktⁿ with n close to 0.25 was obtained, indicating a more complex, diffusion limited, electrochemical reaction at the interface than previously reported     

The spreading resistance of MOSFET's

A simple mathematical expression for source and drain spreading resistance near the channel end of MOSFET's has been derived by calculating the capacitance of the same geometry, using the analogy between the resistivity of conductors and the permittivity of dielectrics (R = ρε/C). Furthermore, it is shown qualitatively and experimentally that the value of the resistivity, which is the most influential parameter in the equation derived, should be determined by a doping concentration equal to the inversion channel carrier concentration, rather than by the source and drain bulk properties.     

一种适用于短沟道LDD MOSFET参数提取的改进方法

提出了一种适用于短沟道LDD MOSFET的改进型参数提取方法,通过对栅偏压范围细分后采用线性回归方法,提取偏压相关参数,保证了线性回归方法的精度和有效性,避免了对栅偏压范围的优化和误差考虑.提取出的参数用于已建立的深亚微米LDD MOSFET的I-V特性模型中,模拟与测试数据的吻合表明了该方法的实用性.     

A new approach to determine the drain-and-source series resistanceof LDD MOSFET's

A method for determining the intrinsic drain-and-source series resistance and the effective channel length of LDD MOSFET's is proposed. The method is based on the experimentally measured device I-V characteristics and a new parameter extraction procedure. A consistent set of the effective channel length and the gate-voltage-dependent drain-and-source series resistance was thus determined. The comparison between the measured and experimental drain current characteristics shows excellent agreement using the present model values     

A comprehensive study of hot-carrier instability in p- and n-typepoly-Si gated MOSFET's

A comprehensive comparison of hot-carrier instability between p- and n-type poly Si-gated MOSFET's is presented in this paper. The electron trapping and interface state generation in the 7 nm gate oxide of MOSFET's are investigated using uniform hot-electron injection from a buried junction injector (BJI) and channel-hot-carrier stress. From BJI experiments, electron trapping (instead of oxide trap generation) and interface state generation are shown to be the major effects of hot-electron injection. Electron trapping and interface state generation are found to be similar in both p- and n-type poly-Si gated MOSFET's. The dependences of interface state generation by hot electrons on oxide voltages and temperatures are observed to be similar between n- and p-type poly-Si gated MOSFET's. From the results of channel-hot-carrier stress on surface-channel n- and p-channel MOSFET's, it was also found that the channel-hot-carrier instabilities of p- and n-type poly-Si gated MOSFET's are comparable