Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

An a-Si:H/a-Si,Ge:H bulk barrier phototransistor with a-SiC:Hbarrier enhancement layer for high-gain IR optical detector

The design and fabrication of a high-gain amorphous silicon/amorphous silicon germanium (a-Si:H/a-Si,Ge:H) bulk barrier phototransistor for infrared light detection applications are reported. The a-Si,Ge:H material featured a lower energy gap and is suitable for the absorption of longer wave light, but it also leads to a low breakdown voltage and high dark current. An additional a-SiC:H thin-film layer was used at the collector/base interface in the conventional amorphous bulk barrier phototransistor to enhance the function of the bulk barrier and obtain high optical gain     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

A novel current-scaling a-Si:H TFTs pixel electrode circuit for AM-OLEDs

Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with a function of current scaling is proposed for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current mirror pixel electrode circuit, in this circuit a high data-to-organic light-emitting device (OLED) current ratio can be achieved, without increasing the a-Si:H TFT size, by using a cascade structure of storage capacitors. Moreover, the proposed circuit can compensate for the variations of TFT threshold voltage. Simulation results, based on a-Si:H TFT and OLED experimental data, showed that a data-to-OLED current ratio larger than 10 and a fast pixel programming time can be accomplished with the proposed circuit.     

Amorphous-Si emitter heterojunction UHF power transistors for handytransmitter

A UHF silicon heterojunction bipolar power transistor with a heavily doped amorphous-silicon emitter is reported. The fabrication process utilized an improved glow discharge technique. The deposition rate of amorphous silicon is 0.3-0.4 Å/s, which is slower than that of conventional a-Si:H. The average carrier density in the amorphous-silicon film is estimated to be about 1.5×10¹⁹ cm^-3. The present device can deliver 4.0-W output power with 72% collector efficiency and 8.2-dB gain at 470 MHz for 9.0-V low supply voltage. These preliminary results make the use of n⁺ a-Si:H as a wide-bandgap emitter material for high-frequency and high-power heterojunction bipolar transistors (HBTs) very attractive     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Electrophotographic patterning of thin-film silicon on glass foil

We report the patterning of thin films of amorphous silicon (a-Si:H) using electrophotographically applied toner as the etch mask. Using a conventional xerographic copier, a toner pattern was applied to 0.1 μm thick a-Si:H films deposited on ~50 μm thick glass foil. The toner then served as the etch mask for a-Si:H, and as the lift-off material for the patterning of chromium. This technique opens the prospect of roll-to-roll, high-throughput patterning of large-area thin-film circuits on glass substrates     

Enhancing the Selectivity and Transparency of the Electron Contact in Silicon Heterojunction Solar Cells by Phosphorus Catalytic Doping

An intrinsic hydrogenated amorphous silicon (a-Si:H(i)) film and a doped silicon film are usually combined in the heterojunction contacts of silicon heterojunction (SHJ) solar cells. In this work, a post-doping process called catalytic doping (Cat-doping) on a-Si:H(i) is performed on the electron selective side of SHJ solar cells, which enables a device architecture that eliminates the additional deposition of the doped silicon layer. Thus, a single phosphorus Cat-doping layer combines the functions of two other layers by enabling excellent interface passivation and high carrier selectivity. The overall thinner layer on the window side results in higher spectral response at short wavelengths, leading to an improved short-circuit current density of 40.31 mA cm⁻² and an efficiency of 23.65% (certified). The cell efficiency is currently limited by sputter damage from the subsequent transparent conductive oxide fabrication and low carrier activation in the a-Si:H(i) with Cat-doping. Numerical device simulations show that the a-Si:H(i) with Cat-doping can provide sufficient field effect passivation even at lower active carrier concentrations compared to the as-deposited doped layer, due to the lower defect density.     

A study of frequency response in silicon heterojunction bipolartransistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (a-Si:H) is incorporated into a two-dimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBT's) with a-Si:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in a-Si:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor, We find that an electron drift mobility of at least 100 cm² V^-1 s^-1 is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm ² V^-1 s^-1 and heteroemitter doping of 5×10¹⁷ cm^-3, a maximum cutoff frequency of 52 GHz can be expected     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

Ion beam synthesis of low resistivity contacts in amorphous silicon-based materials

Low resistivity layers have been formed at low process temperatures, by high dose Co⁺ ion implantation in to hydrogenated amorphous silicon (a-Si:H) and amorphous silicon carbide (a-SiC:H). The lowest resistivities, of the order of 10 ohms/Sq, have been observed for the carbon-free films (a-Si:H) and can be obtained at annealing temperatures of <250°C. Schottky barrier contacts to the a-Si:H films exhibit near ideal behavior with low leakage currents, of the order 10⁻⁹ A·cm⁻². The electrical properties of the amorphous films are assessed as a function of ion dose, dose rate and annealing conditions, with a view to optimizing these parameters.     

High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

Amorphous silicon thin-film transistor with fluorinated siliconoxide ion stopper

We propose fluorinated silicon oxide (SiOF) as the ion-stopper of bottom-gate amorphous silicon thin film transistors (a-Si:H TFTs). The low dielectric constant SiOF on both the back-channel of the TFT and the crossover regions of gate/data lines can contribute to reducing the RC delay of the gate pulse signal in active-matrix liquid-crystal displays. Besides, the a-Si:H TFT with a SiOF stopper shows an improved performance compared to the widely-employed silicon nitride (SiN_x ) stopper TFT, because the fluorine incorporation reduces the interface state density between a-Si:H and SiOF     

Thick-layered etched-contact amorphous silicon transistors

We introduce a new thick-layered, etched-contact a-Si:H TFT (TLEC-TFT) structure which allows the use of thick a-Si:H layers without increasing the TFT contact resistance. This device facilitates the integration of high-performance TFTs and thick-layered photo-transistors in a-Si:H-based image sensors. The TLEC-TFT is fully compatible with the conventional TFT fabrication process and requires no extra masking steps. For low values of the drain-to-source voltage, our new TFT boosts the linear region current by two orders of magnitude over that of conventional TFTs with identically thick a-Si:H layers. By removing the adverse effects of contact resistance in transistors with thick a-Si:H layers, our TLEC-TFT design allows us to compare the performance of TFTs with thick and thin a-Si:H layers. We find that the width of the conduction-band tail decreases in thick-layered a-Si:H TFTs. This reduction in the width of the band tails results in an increase in the TFT mobility and subthreshold slope. Consequently, thick-layered, etched-contact TFTs possess higher overall current-drive capabilities compared to conventional, thin-layered TFTs. We present experimental evidence which correlates the width of the conduction-band tail to the density of as-deposited free carriers     

α-Si-H TFT及有源矩阵选址平板液晶显示

本文报道了用于平板液晶显示(LCD)的氢化非晶硅薄膜晶体管(α-Si:H TFT)的研制结果,此晶体管开态电流约10~(-6)A,关态电流<10~(-11)A,开启电压～15V.用此α-Si:H TFT矩阵已封装出具有20×20个有效象素单元的液晶显示平板,并成功地实现了有源选址与动态显示功能.同时,对如何进一步提高TFT性能作了一些分析与讨论.     

a-Si:H/a-SiN_x:H多层膜界面的研究

<正> 尽管过去几年对非晶半导体多层膜及其界面对多层膜传输性能影响的研究甚多,然而对于界面缺陷态的特性及其密度了解甚少。不同的测量方法得到的a-Si:H/a-SiNx:H界面缺陷态密度可从1010变到1012cm-2。这一实验结果反映了每一测试方法仅能探测某些能级的缺陷,在某些情况下可能是不同类的缺陷。非晶硅系材料都包含有氢。已发现,在多层膜的沉积过程中,由于组成多层膜的子层间应力释放的需要以及两子层材料的氢扩散系数不同而     

Characteristics of Cr Schottky amorphous silicon photodiodes andtheir application to linear image sensors

Cr Schottky amorphous silicon (a-Si:H) photodiodes with a configuration of Cr/a-Si:H tin-doped indium oxide (ITO), where Cr is negatively biased with respect to ITO in contrast to the conventional bias direction, were characterized to provide simple and stable sensor elements for economical linear image sensors. It was found that the barrier height of the Cr/a-Si:H junction is sufficiently high (0.89 eV) to prevent electron injection and that the junction is thermally stable. The transport properties of holes propagating in the a-Si:H layer were largely improved by a few parts per million boron doping, and as a result saturation of the photocurrent was achieved. A contact-type ISO A4, 8-dot/mm linear range sensor was fabricated using the Cr Schottky photodiode array. The sensor showed excellent characteristics for use in G3 facsimile     

a-SiH 热处理过程中纳米硅粒尺寸的控制(英文)

报道了控制热处理过程中含氢非晶硅中纳米硅颗粒大小的一种新方法。用喇曼散射、X射线衍射和计算机模拟,发现在非晶硅中所形成的纳米硅颗粒的大小,随着热退火过程中升温速率的变化而变化。在退火过程中,若非晶硅薄膜升温速率较高(～100℃/s),则所形成纳米硅粒的大小在1.6～15nm;若非晶硅薄膜升温速率较低(～1℃/s),则纳米硅粒大小在23～46nm。根据晶体生长理论,讨论了升温速率的高低与所形成的纳米硅颗粒大小的关系。     

High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications

A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is developed in this letter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts of source/drain metal and the sidewall of a-Si:H island edge. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility as high as 1.05 cm/sup 2//Vs, due to the enormous improvement in parasitic resistance. The impressively high performance of the proposed a-Si:H TFT provides the potential to apply foractive matrix liquid crystal display and active matrix organic light-emitting diode technology.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V