A study of analog decision feedback equalization for ADC-Based serial link receivers

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.     

A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC

A low-voltage low-power small-area and high-resolution digital-to-analog converter (DAC) for mixed-signal applications is Introduced. A binary weighted current steering DAC is a power-efficient architecture, because almost all the current taken from the supply is used for the output signal. The current steering architecture is also highly suitable for high-speed operation. Typically, the architecture suffers from poor linearity characteristics, but the problem can be prevented with a novel calibration method, where the currents generated for the most significant bits are fine tuned. As a result, a very compact and low-power solution can be implemented by using a low-voltage digital technology     

New transmit schemes and simplified receivers for MIMO wireless communication systems

In this paper, optimized transmit schemes for multiple-input multiple-output (MIMO) systems with simplified receivers are proposed for the downlink of high-speed wireless communication systems. In these systems, MIMO signal preprocessing is performed at the transmitter or base station with the receiver at the mobile station having a simplified structure that requires only limited signal processing. An important potential application for our transmit MIMO techniques is in the downlink of high-speed wireless communication systems with Vertical Bell Laboratories Layered Space-Time (V-BLAST) or a similar technique utilized in the uplink, creating a high-speed duplex system with a simplified mobile station transceiver structure. Two approaches are introduced and these depend on whether or not receive diversity is employed at the receiver. Both methods require that channel state information be available at the transmitter. In addition, some important associated issues such as peak-to-average power ratio requirements at the transmitter and robustness to downlink channel errors are also investigated and various solutions are proposed. Simulation results are provided and these show that performance improvement can be achieved when compared with other MIMO transmit schemes.     

双信号单通道红外光传输

以FPGA作为控制核心,设计了一种脉冲频率调制(PFM)与脉冲宽度调制(PWM)对信号先后调制,并用红外光来进行同时传输的装置。发送端通过FPGA自带的高速AD对音频信号采样,通过PFM与PWM来实现音频信号的调制,接收端FPGA对光脉冲进行解调输出。设计中发射电路与接收电路完全采用分离元件进行构建,具有成本低、功耗小、传输效率高等优点。通过对设计结果的分析可以得到在12 m内,1～10 kHz的音频信号和数字信号能够在一个通道里进行无失真的实时传输。传输信号经过中继站实现信号向不同方向转发的功能。同时中继站的功耗为0.08 W,满足节能的要求。     

Low-power equalizer architectures for high speed modems

In many DSP-based high-speed modem applications, such as broadband modems for high-speed Internet access to the home or gigabit Ethernet transceivers, channel equalization requires processing power so high that power consumption and clock speed become major design challenges. This article describes techniques to implement low-cost adaptive equalizers for ASIC implementations of broadband modems. Power consumption can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techniques. The derivation of a hybrid FIR filter structure is given that enables the designer to adjust both the speed and power consumption to suit an application. Furthermore, the architecture can be made programmable to target multiple applications in one piece of silicon while maintaining or even improving the efficiency of the architecture. Run-time techniques are shown that can minimize the power consumption for a given application or operating environment. In all cases, the power reduction techniques are supported by simulations and measurements made on a test integrated circuit     

短波单载波空时分组码的频域均衡研究

短波通信受多径衰落、干扰复杂等影响严重。空时分组码(Space Time Block Code,STBC)技术在无需增加频谱资源和天线发射功率的前提下,可以利用多输入多输出(Multiple-Input Multiple-Output,MIMO)信道提供的分集增益提升传输可靠性。分析短波MIMO研究现状,提出短波单载波STBC频域均衡(Frequency-Domain Equalization,FDE)系统架构,针对短波信道引入的码间干扰研究MIMO MMSE-FDE均衡技术,并将单载波STBC频域均衡与时域均衡及短波现有波形进行仿真对比。仿真结果表明,相较于短波现有波形,单载波STBC频域均衡系统的可靠性有较大幅度提升,且性能与STBC时域均衡接近,但计算复杂度远低于STBC时域均衡。     

A CMOS two-path tree search detector

Two-path tree search (TPTS) is a detection algorithm combining a decision-feedback equalizer and a two-path tree search estimator. This sub-optimal tree search overcomes the exponential increase in hardware complexity with tree length in a fixed-delay tree search structure. An adaptive mixed-signal CMOS TPTS detector is presented in this paper. The integrated circuit occupies 2.77 mm by 2.44 mm (including the bonding pads) in a 0.6 μm CMOS process. It performs about 0.8 dB better than a conventional decision-feedback equalization for a disk drive read channel     

A NOVEL PHYSICAL-LAYER TRANSCEIVER USED IN USB2.0 SERIAL DATA LINK

The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus （USB） 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve precision of received data. The circuit simulation is based on Cadence＇s spectre software and Taiwan Semiconductor Manufacture Corporation＇s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor （CMOS） model. The front and post-simulation results reveal that the transceiver designed can transmit and receive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physical-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.     

Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps

This paper presents a new design technique of high-speed interconnects with controlled intersymbol interference (ISI) to create efficient signaling over a band-limited channel. Performance of high-speed electrical links is limited by conductor loss, dielectric dispersion, and reflections in the board, package, and connector. These nonidealities result in significant ISI. In current systems, the effect of ISI is either mitigated through complex equalization, signal conditioning, and coding techniques, or through costly impedance control and manufacturing processes. In the proposed approach, instead of eliminating ISI, we shape the response of the channel into a set of channel characteristics with controlled ISI using simple passive structures in the board and the package. The resulting controlled ISI is exploited at the transmitter and receiver to simplify the architecture of the system and to achieve high data rates. The techniques to design interconnects with controlled ISI are reasonably simple to implement in conventional interconnect technologies. Simulation examples are given to demonstrate the validity and advantages of the design technique using duobinary and analog multitone (AMT) signaling methods.      

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.     

A Mixed-Signal Equalizer Structure for Magnetic Storage Read Channels

Design techniques for read channel equalizers used in magnetic recording systems are presented. The equalization is based on a multi-level dual decision feedback architecture. The signal processing at low power and high speed is realized by using a continuous-time adaptive forward filter with an infinite impulse response. Furthermore, circuit structures with reduced offset-voltage sensitivities are developed for the equalizer implementation. As a result, the data rate in the intended application can be greater than 200 Mbits/s.     

A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSPusing partial response signaling with maximum likelihood detection

A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper. PR-IV (minimum signal bandwidth) for signal encoding is used, along with ML (maximum likelihood) detection to achieve superior error rate performance. Signal equalization is provided using a programmable ten-tap FIR (finite impulse response) digital filter. This read/write channel is implemented on a single chip using analog circuits and 20 K CMOS logic gates. The 7.5 mm square chip uses a 5 V, 1 μm, BiCMOS process with a 6 GHz n-p-n and a 1 GHz p-n-p and is packaged in a 100-lead metal QFPK (quad flat pack)     

A channel unit signal controller for shared codec D-type channel banks

The channel unit signal controller is a 2.56 mm/spl times/2.56 mm beam-leaded silicon integrated circuit fabricated using the complementary bipolar integrated circuit (CBIC) technology with buried injector logic (BIL). The circuit handles the distribution of signals within a channel unit of a digital telecommunications system. Several diverse circuit functions are incorporated on this device including high-speed emitter-coupled logic, lower speed buried injector logic. JFET switches, high-speed pulse amplifiers to drive the JFETs, a voltage limiter, and a comparator circuit. The channel unit signal controller is described from system and circuit points of view and the CBIC/BIL process is described.     

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with 'OR' logic for dual-modulus operation,the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process.The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.     

Modeling and Analysis of High-Speed I/O Links

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.      

单片集成TFT-LCD驱动芯片的设计验证策略

混合信号VLSI芯片的单片特性验证是此类芯片的设计难题之一.针对典型的混合信号VLSI芯片--单片集成薄膜晶体管液晶显示器(TFT-LCD)驱动芯片,设计了一种能够直观模拟液晶显示的系统级验证平台,并利用此验证平台验证了系统架构的正确性.还针对此芯片的设计特点,结合系统验证平台为整个设计流程的各个阶段提出了不同的验证策略.通过对这些策略的配合使用,对芯片特性进行了全面验证,包括模块级验证、芯片级验证以及物理验证.该验证策略具有高效、直观、可靠等特点.     

双选择性信道下发射分集MISO OFDM系统基于BEM的低复杂度信道均衡

在高速移动环境下,无线信道会同时经历时间选择性和频率选择性衰落,即所谓的快速时变信道,也称之为双选择性信道。最初的发射分集Alamouti编码方案是针对时不变平坦信道提出的,不能直接应用于快速时变信道。此外,OFDM 系统在双选信道下遭受的载波间干扰(ICI)不可忽视。因此,发射分集MISO OFDM系统在双选择性信道下既节能又有效的信号恢复是有挑战的。本文基于双选择性信道的基扩展模型(BEM)表示,研究了一种有效的可动态分组的混合干扰消除(HIC)信道均衡方案。仿真结果表明,提出的方案,与传统的MMSE均衡相比,计算复杂度大大降低的同时性能显著提高,计算量的降低减少了能量消耗,达到节能的目的;与现有的关于发射分集的信道均衡方案相比,表现出性能和复杂度的较好折中;此外,在信道信息完美已知的假设下,随着移动速度的提高,误码性能没有损失。      

A 256-element CMOS imaging receiver for free-space optical communication

This paper describes a CMOS imaging receiver for free-space optical (FSO) communication. The die contains 256 optical receive channels with -47 dBm optical sensitivity and 30 dB optical dynamic range at 500 kb/s/channel while consuming 67 mW. Received signals are amplified by digitally self-calibrated open-loop amplifiers and digitized before clock and data recovery. The sampled data also provide inputs for digital automatic gain and offset control loops closed around the analog amplifier chain to compensate for signal variations due to atmospheric turbulence and daylight interference. Gain control logic can adapt to incident signals over the 30 dB dynamic range within 28 bit periods. Low-power logic design and analog circuit techniques are used to minimize digital crosstalk to single-ended photodetectors referenced to a bulk substrate. Local arbitration circuitry at each channel forms an intrachip data passing network to multiplex received data words from the 16 /spl times/ 16 array onto a common off-chip bus. The 1.6 M transistor mixed-signal die fabricated in a 0.25 /spl mu/m CMOS process measures 6.5/spl times/6.5 mm/sup 2/. Reception at 500 kb/s through a 1.5 km atmospheric channel is demonstrated with 3 mW optical transmit power during nighttime and daylight hours.     

Separation of cochannel GSM signals using an adaptive array

The Global System for Mobile communications (GSM) is a digital cellular radio network that employs time division multiple access (TDMA). In such a cellular system, frequencies are reused in different regions for spectral efficiency, and thus, the transmissions in a given cell can interfere with those in distant cells. This cochannel interference can be a major impairment to the signal of interest. In this paper, we describe a beamformer and equalizer system that is capable of separating and demodulating several cochannel GSM signals. The signal model includes intersymbol interference (ISI) induced by the Gaussian transmit filter, and the channel model incorporates multipath propagation and additive white Gaussian noise. The GSM synchronization sequences are used to compute the beamformer weights and achieve frame synchronization simultaneously. Decision-feedback equalization is employed to compensate for the transmit filter ISI and to demodulate the data     

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-/spl mu/m CMOS process, the 1.9-mm/sup 2/ transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2/sup 23/-1 PRBS input data with 800-ppm frequency offset.